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[security,check_regwen] Add regwen countermeasure check #6383

[security,check_regwen] Add regwen countermeasure check

[security,check_regwen] Add regwen countermeasure check #6383

Triggered via pull request February 21, 2025 05:38
Status Success
Total duration 33m 0s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW310  /  Build bitstream
3m 1s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
2m 45s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
3m 5s
Earl Grey for CW310 Hyperdebug / Build bitstream
Lint (slow)
11m 6s
Lint (slow)
Build documentation
5m 13s
Build documentation
Airgapped build
10m 36s
Airgapped build
Verible lint
1m 3s
Verible lint
Run OTBN smoke Test
2m 35s
Run OTBN smoke Test
Run OTBN crypto tests
21m 57s
Run OTBN crypto tests
Verilated English Breakfast
3m 36s
Verilated English Breakfast
Verilated Earl Grey
3m 38s
Verilated Earl Grey
CW305's Bitstream
2m 53s
CW305's Bitstream
Build Docker Containers
2m 18s
Build Docker Containers
Build and test software
24m 58s
Build and test software
Build and test Darjeeling software
3m 43s
Build and test Darjeeling software
QEMU smoketest
2m 31s
QEMU smoketest
CW310 Test ROM Tests  /  FPGA test
2m 31s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
4m 4s
CW310 ROM Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
1m 58s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
53s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
3m 39s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
3m 19s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
2m 56s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
4m 9s
CW340 Manufacturing Tests / FPGA test
Hyper310 ROM_EXT Tests  /  FPGA test
2m 52s
Hyper310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
4m 15s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
5m 30s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
3m 52s
CW310 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
32s
Verify FPGA jobs
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Annotations

3 errors
Verilated English Breakfast
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.38 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
59.3 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
56 KB
execute_rom_ext_fpga_tests_cw310-targets
598 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
31.1 KB
execute_rom_ext_fpga_tests_cw340-targets
427 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.1 KB
execute_rom_fpga_tests_cw310-targets
1.73 KB
execute_rom_fpga_tests_cw310-test-results
46.2 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
37.7 KB
execute_sival_fpga_tests_cw340-targets
514 Bytes
execute_sival_fpga_tests_cw340-test-results
41.4 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.27 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
187 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
449 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
18.9 KB
execute_test_rom_fpga_tests_cw310-targets
326 Bytes
execute_test_rom_fpga_tests_cw310-test-results
3.29 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
45.4 KB
partial-build-bin-chip_earlgrey_cw310
5.99 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
5.99 MB
partial-build-bin-chip_earlgrey_cw340
10 MB
sw_build_test-test-results
73.9 KB
verilated_englishbreakfast
7.03 MB
verilator_earlgrey-test-results
9.15 KB