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[prim,clkmgr,rtl] Simplify prim_clock_meas by removing RefCnt #6372

[prim,clkmgr,rtl] Simplify prim_clock_meas by removing RefCnt

[prim,clkmgr,rtl] Simplify prim_clock_meas by removing RefCnt #6372

Triggered via pull request February 20, 2025 17:56
Status Success
Total duration 6h 48m 13s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW340  /  Build bitstream
1h 29m
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
1h 4m
Earl Grey for CW310 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 3m
Earl Grey for CW310 Hyperdebug / Build bitstream
Lint (slow)
11m 26s
Lint (slow)
Build documentation
5m 34s
Build documentation
Airgapped build
10m 27s
Airgapped build
Verible lint
1m 16s
Verible lint
Run OTBN smoke Test
3m 9s
Run OTBN smoke Test
Run OTBN crypto tests
2m 44s
Run OTBN crypto tests
Verilated English Breakfast
8m 4s
Verilated English Breakfast
Verilated Earl Grey
1h 12m
Verilated Earl Grey
CW305's Bitstream
24m 24s
CW305's Bitstream
Build Docker Containers
2m 22s
Build Docker Containers
Build and test software
19m 18s
Build and test software
Build and test Darjeeling software
4m 7s
Build and test Darjeeling software
QEMU smoketest
2m 26s
QEMU smoketest
CW340 Test ROM Tests  /  FPGA test
4m 52s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
50s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
6m 41s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
19m 23s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
4m 0s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
42m 19s
CW340 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
3m 55s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
38m 7s
CW310 ROM Tests / FPGA test
Hyper310 ROM_EXT Tests  /  FPGA test
13m 53s
Hyper310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
22m 33s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
32m 57s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
29m 49s
CW310 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
24s
Verify FPGA jobs
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3 errors
Verilated English Breakfast
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.38 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
59.8 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
55.7 KB
execute_rom_ext_fpga_tests_cw310-targets
598 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
31.3 KB
execute_rom_ext_fpga_tests_cw340-targets
427 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.01 KB
execute_rom_fpga_tests_cw310-targets
1.73 KB
execute_rom_fpga_tests_cw310-test-results
45.9 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
38 KB
execute_sival_fpga_tests_cw340-targets
514 Bytes
execute_sival_fpga_tests_cw340-test-results
41.5 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.27 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
187 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
449 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
19.8 KB
execute_test_rom_fpga_tests_cw310-targets
326 Bytes
execute_test_rom_fpga_tests_cw310-test-results
3.28 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
45.3 KB
partial-build-bin-chip_earlgrey_cw310
5.99 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
5.99 MB
partial-build-bin-chip_earlgrey_cw340
10 MB
sw_build_test-test-results
74 KB
verilated_englishbreakfast
7.03 MB
verilator_earlgrey-test-results
9.07 KB