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[signing] Implement owner-stage signing #2859

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[signing] Implement owner-stage signing

[signing] Implement owner-stage signing #2859

Triggered via pull request December 5, 2024 06:47
@cfrantzcfrantz
synchronize #25506
cfrantz:a1-owner-signing
Status Failure
Total duration 2h 7m 49s
Artifacts 33

ci.yml

on: pull_request
Lint (quick)
3m 17s
Lint (quick)
Earl Grey for CW340  /  Build bitstream
1h 29m
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 9m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
1h 11m
Earl Grey for CW310 / Build bitstream
Lint (slow)
13m 42s
Lint (slow)
Airgapped build
13m 23s
Airgapped build
Verible lint
1m 1s
Verible lint
Run OTBN smoke Test
2m 31s
Run OTBN smoke Test
Run OTBN crypto tests
2m 51s
Run OTBN crypto tests
Verilated English Breakfast
7m 31s
Verilated English Breakfast
Verilated Earl Grey
1h 25m
Verilated Earl Grey
CW305's Bitstream
21m 50s
CW305's Bitstream
Build Docker Containers
2m 42s
Build Docker Containers
Build and test software
13m 5s
Build and test software
CW340 Test ROM Tests  /  FPGA test
53s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
6m 13s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
52s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
4m 26s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
48s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
5m 44s
CW340 Manufacturing Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
30m 56s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
33m 52s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
29m 7s
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
15m 15s
CW310 ROM_EXT Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
6m 8s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
26m 49s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
5m 0s
CW310 ROM_EXT Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
30s
Verify FPGA jobs
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Annotations

3 errors
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 127.
Verify FPGA jobs
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.34 MB
execute_fpga_rom_ext_tests_cw310-targets
618 Bytes
execute_fpga_rom_ext_tests_cw310-test-results
47.3 KB
execute_manuf_fpga_tests_cw310-targets
608 Bytes
execute_manuf_fpga_tests_cw310-test-results
42.6 KB
execute_manuf_fpga_tests_cw340-targets
266 Bytes
execute_manuf_fpga_tests_cw340-test-results
4.52 KB
execute_rom_ext_fpga_tests_cw310-targets
325 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
2.56 KB
execute_rom_ext_fpga_tests_cw340-targets
162 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
200 Bytes
execute_rom_fpga_tests_cw310-targets
1.8 KB
execute_rom_fpga_tests_cw310-test-results
45.1 KB
execute_rom_fpga_tests_cw340-targets
261 Bytes
execute_rom_fpga_tests_cw340-test-results
19.8 KB
execute_sival_fpga_tests_cw310-targets
931 Bytes
execute_sival_fpga_tests_cw310-test-results
68.5 KB
execute_sival_fpga_tests_cw340-targets
247 Bytes
execute_sival_fpga_tests_cw340-test-results
2.36 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.35 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
171 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
162 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
200 Bytes
execute_test_rom_fpga_tests_cw310-targets
372 Bytes
execute_test_rom_fpga_tests_cw310-test-results
52.6 KB
execute_test_rom_fpga_tests_cw340-targets
162 Bytes
execute_test_rom_fpga_tests_cw340-test-results
200 Bytes
partial-build-bin-chip_earlgrey_cw310
6.01 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6 MB
partial-build-bin-chip_earlgrey_cw340
9.46 MB
sw_build_test-test-results
58.3 KB
verilated_englishbreakfast
6.36 MB
verilator_earlgrey-test-results
8.8 KB