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merge #1
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@lonkaars
lonkaars committed Feb 14, 2023
1 parent 060325a commit c1d77b6
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Showing 4 changed files with 93 additions and 7 deletions.
4 changes: 4 additions & 0 deletions .gitignore
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Expand Up @@ -18,3 +18,7 @@ copyright/

# drawio
**/.$*

# vivado troep
*.log
*.jou
6 changes: 4 additions & 2 deletions keyboard/keyboard.xpr
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Expand Up @@ -197,16 +197,17 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="19">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
Expand All @@ -219,6 +220,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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26 changes: 24 additions & 2 deletions src/dispshift.vhd
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Expand Up @@ -11,7 +11,29 @@ end dispshift;

architecture Behavioral of dispshift is

begin

-- init as empty display
signal sD: std_logic_vector(11 downto 0) := x"aaa";
signal SLastValue: std_logic := '0';

begin
process(CLK)
begin
if (rising_edge (clk)) then
-- set default values
SLastValue <= S;
sD <= sD;

-- when S does go high update output
if (SLastValue = '0' and S = '1') then
-- set data on output
N3 <= sD(11 downto 8);
N2 <= sD(7 downto 4);
N1 <= sD(3 downto 0);
N0 <= D;

-- store new data
sD <= sD(7 downto 0) & D;
end if;
end if;
end process;
end Behavioral;
64 changes: 61 additions & 3 deletions src/scancodefilter.vhd
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@@ -1,6 +1,6 @@
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.numeric_std.all;

entity scancodefilter is port(
CLK: in std_logic; -- system clock
Expand All @@ -12,7 +12,65 @@ end scancodefilter;

architecture Behavioral of scancodefilter is

begin

-- init as empty key
--signal lastKey: std_logic_vector(3 downto 0) := x"a";
signal lastNEW_DAT: std_logic := '0';
signal DAT_OLD: std_logic_vector(7 downto 0); -- scancode preveouse input

begin
process(CLK)
begin
if (rising_edge (clk)) then
-- always set data on output
BCD <= x"a";
SHIFT <= '0';
lastNEW_DAT <= NEW_DAT;
DAT_OLD <= DAT_OLD;

-- when NEW_DAT does go high
if ((lastNEW_DAT = '0') and (NEW_DAT = '1')) then
-- set DAT_OLD
DAT_OLD <= DAT;

-- only is pervioause data is not release of key scancode and currend data
if (DAT_OLD /= x"F0" and DAT /= x"F0") then
case DAT is
when x"45" =>
BCD <= std_logic_vector(to_unsigned(0, BCD'length));
SHIFT <= '1';
when x"16" =>
BCD <= std_logic_vector(to_unsigned(1, BCD'length));
SHIFT <= '1';
when x"1E" =>
BCD <= std_logic_vector(to_unsigned(2, BCD'length));
SHIFT <= '1';
when x"26" =>
BCD <= std_logic_vector(to_unsigned(3, BCD'length));
SHIFT <= '1';
when x"25" =>
BCD <= std_logic_vector(to_unsigned(4, BCD'length));
SHIFT <= '1';
when x"2E" =>
BCD <= std_logic_vector(to_unsigned(5, BCD'length));
SHIFT <= '1';
when x"36" =>
BCD <= std_logic_vector(to_unsigned(6, BCD'length));
SHIFT <= '1';
when x"3D" =>
BCD <= std_logic_vector(to_unsigned(7, BCD'length));
SHIFT <= '1';
when x"3E" =>
BCD <= std_logic_vector(to_unsigned(8, BCD'length));
SHIFT <= '1';
when x"46" =>
BCD <= std_logic_vector(to_unsigned(9, BCD'length));
SHIFT <= '1';
when others =>
BCD <= x"b";
SHIFT <= '1';
end case;
end if;
end if;
end if;
end process;
end Behavioral;

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