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Add script for decoding and encoding clock configuration
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,119 @@ | ||
| { | ||
| "afc_ver": "3.1", | ||
| "in_cfg": { | ||
| "FMC2_CLK3_BIDIR": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC2_CLK1_M2": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC2_CLK0_M2C": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC2_CLK2_BIDIR": { | ||
| "POL": "POS" | ||
| }, | ||
| "TCLKB": { | ||
| "POL": "POS" | ||
| }, | ||
| "TCLKA": { | ||
| "POL": "POS" | ||
| }, | ||
| "TCLKC": { | ||
| "POL": "POS" | ||
| }, | ||
| "TCLKD": { | ||
| "POL": "POS" | ||
| }, | ||
| "FCLKA": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC1_CLK3_BIDIR": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC1_CLK1_M2C": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC1_CLK0_M2C": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC1_CLK2_BIDIR": { | ||
| "POL": "POS" | ||
| }, | ||
| "WR_PLL_CLK1": { | ||
| "POL": "POS" | ||
| }, | ||
| "CLK20_VCXO": { | ||
| "POL": "POS" | ||
| }, | ||
| "SI57X_CLK": { | ||
| "POL": "POS" | ||
| } | ||
| }, | ||
| "out_cfg": { | ||
| "TCLKD": { | ||
| "SRC": "FMC2_CLK3_BIDIR", | ||
| "EN": false | ||
| }, | ||
| "TCLKC": { | ||
| "SRC": "FMC2_CLK3_BIDIR", | ||
| "EN": false | ||
| }, | ||
| "TCLKA": { | ||
| "SRC": "FMC2_CLK3_BIDIR", | ||
| "EN": false | ||
| }, | ||
| "TCLKB": { | ||
| "SRC": "FMC2_CLK3_BIDIR", | ||
| "EN": false | ||
| }, | ||
| "FPGA_CLK1": { | ||
| "SRC": "WR_PLL_CLK1", | ||
| "EN": true | ||
| }, | ||
| "FP2_CLK2": { | ||
| "SRC": "FCLKA", | ||
| "EN": false | ||
| }, | ||
| "LINK01_CLK": { | ||
| "SRC": "TCLKA", | ||
| "EN": true | ||
| }, | ||
| "FP2_CLK1": { | ||
| "SRC": "SI57X_CLK", | ||
| "EN": true | ||
| }, | ||
| "PCIE_CLK1": { | ||
| "SRC": "FCLKA", | ||
| "EN": true | ||
| }, | ||
| "LINK23_CLK": { | ||
| "SRC": "TCLKA", | ||
| "EN": false | ||
| }, | ||
| "FIN1_CLK3": { | ||
| "SRC": "TCLKA", | ||
| "EN": true | ||
| }, | ||
| "FIN1_CLK2": { | ||
| "SRC": "TCLKA", | ||
| "EN": true | ||
| }, | ||
| "RTM_SYNC_CLK": { | ||
| "SRC": "CLK20_VCXO", | ||
| "EN": false | ||
| }, | ||
| "OP15C": { | ||
| "SRC": "TCLKA", | ||
| "EN": true | ||
| }, | ||
| "FIN2_CLK2": { | ||
| "SRC": "TCLKA", | ||
| "EN": true | ||
| }, | ||
| "FIN2_CLK3": { | ||
| "SRC": "TCLKA", | ||
| "EN": true | ||
| } | ||
| } | ||
| } |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,119 @@ | ||
| { | ||
| "afc_ver": "3.1", | ||
| "in_cfg": { | ||
| "FMC2_CLK3_BIDIR": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC2_CLK1_M2": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC2_CLK0_M2C": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC2_CLK2_BIDIR": { | ||
| "POL": "POS" | ||
| }, | ||
| "TCLKB": { | ||
| "POL": "POS" | ||
| }, | ||
| "TCLKA": { | ||
| "POL": "POS" | ||
| }, | ||
| "TCLKC": { | ||
| "POL": "POS" | ||
| }, | ||
| "TCLKD": { | ||
| "POL": "POS" | ||
| }, | ||
| "FCLKA": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC1_CLK3_BIDIR": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC1_CLK1_M2C": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC1_CLK0_M2C": { | ||
| "POL": "POS" | ||
| }, | ||
| "FMC1_CLK2_BIDIR": { | ||
| "POL": "POS" | ||
| }, | ||
| "WR_PLL_CLK1": { | ||
| "POL": "POS" | ||
| }, | ||
| "CLK20_VCXO": { | ||
| "POL": "POS" | ||
| }, | ||
| "SI57X_CLK": { | ||
| "POL": "POS" | ||
| } | ||
| }, | ||
| "out_cfg": { | ||
| "TCLKD": { | ||
| "SRC": "FMC2_CLK3_BIDIR", | ||
| "EN": false | ||
| }, | ||
| "TCLKC": { | ||
| "SRC": "FMC2_CLK3_BIDIR", | ||
| "EN": false | ||
| }, | ||
| "TCLKA": { | ||
| "SRC": "FMC2_CLK3_BIDIR", | ||
| "EN": false | ||
| }, | ||
| "TCLKB": { | ||
| "SRC": "SI57X_CLK", | ||
| "EN": true | ||
| }, | ||
| "FPGA_CLK1": { | ||
| "SRC": "SI57X_CLK", | ||
| "EN": true | ||
| }, | ||
| "FP2_CLK2": { | ||
| "SRC": "FCLKA", | ||
| "EN": false | ||
| }, | ||
| "LINK01_CLK": { | ||
| "SRC": "WR_PLL_CLK1", | ||
| "EN": true | ||
| }, | ||
| "FP2_CLK1": { | ||
| "SRC": "FCLKA", | ||
| "EN": false | ||
| }, | ||
| "PCIE_CLK1": { | ||
| "SRC": "FCLKA", | ||
| "EN": true | ||
| }, | ||
| "LINK23_CLK": { | ||
| "SRC": "WR_PLL_CLK1", | ||
| "EN": false | ||
| }, | ||
| "FIN1_CLK3": { | ||
| "SRC": "CLK20_VCXO", | ||
| "EN": false | ||
| }, | ||
| "FIN1_CLK2": { | ||
| "SRC": "CLK20_VCXO", | ||
| "EN": false | ||
| }, | ||
| "RTM_SYNC_CLK": { | ||
| "SRC": "CLK20_VCXO", | ||
| "EN": false | ||
| }, | ||
| "OP15C": { | ||
| "SRC": "SI57X_CLK", | ||
| "EN": true | ||
| }, | ||
| "FIN2_CLK2": { | ||
| "SRC": "CLK20_VCXO", | ||
| "EN": false | ||
| }, | ||
| "FMC2_CLK2_BIDIR": { | ||
| "SRC": "FMC2_CLK2_BIDIR", | ||
| "EN": false | ||
| } | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,101 @@ | ||
| { | ||
| "afc_ver": "4.0", | ||
| "cfg": { | ||
| "AMC_CLK_RTM_CLK": { | ||
| "SRC": "TCLKA", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "OUT" | ||
| }, | ||
| "FMC2_CLK1_M2C_FMC2_CLK3_BIDIR": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "FMC1_CLK1_M2C_FMC1_CLK3_BIDIR": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "FMC1_CLK0_M2C": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "FMC1_CLK2_BIDIR": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "SI57X_PRI": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "ON", | ||
| "DIR": "IN" | ||
| }, | ||
| "FMC2_CLK0_M2C": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "FMC2_CLK2_BIDIR": { | ||
| "SRC": "TCLKA", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "OUT" | ||
| }, | ||
| "TCLKD_FLEX_FPGA_CLK3": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "TCLKC_FLEX_FPGA_CLK2": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "TCLKA": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "ON", | ||
| "DIR": "IN" | ||
| }, | ||
| "TCLKB": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "FLEX_GTP113_CLK0": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "FLEX_GTP113_GTP216_CLK1": { | ||
| "SRC": "SI57X_PRI", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "OUT" | ||
| }, | ||
| "FLEX_GTP116_CLK1_RTM_GTP03": { | ||
| "SRC": "AMC_CLK_RTM_CLK", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "IN" | ||
| }, | ||
| "FLEX_GTP213_CLK1_RTM_GTP47": { | ||
| "SRC": "TCLKA", | ||
| "POL": "POS", | ||
| "TERM": "OFF", | ||
| "DIR": "OUT" | ||
| } | ||
| } | ||
| } |
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