Merge branch 'master' into documenation

.github/workflows/buildDocker.yml

@@ -0,0 +1,50 @@
+# ##############################################################################
+# TODO: Add verification task after the netlist modification
+################################################################################
+
+name: Arch XML Regression
+
+# Run CI on push on each branch
+on:
+  push:
+  pull_request:
+
+jobs:
+  generate_netlist:
+    name: Arch development
+    runs-on: ubuntu-18.04
+    container: ghcr.io/lnis-uofu/openfpga-master:latest
+    strategy:
+      fail-fast: false
+      matrix:
+        config:
+          - name: "FPGA1212_QLSOFA_HD"
+          - name: "FPGA1212_SOFA_CHD"
+          - name: "FPGA1212_SOFA_HD"
+    steps:
+      - name: Runner workspace path
+        run: |
+          echo "Cleaning up previous run"
+          rm -rf "${{ github.workspace }}"
+          mkdir -p "${{ github.workspace }}"
+      - name: Checkout OpenFPGA-ArcticPro3 repo
+        uses: actions/checkout@v2
+      - name: Detect changes
+        uses: technote-space/get-diff-action@v4
+        with:
+          PATTERNS: |
+            ${{ matrix.config.name }}_PNR/*_task/**
+      - name: Running benchmark
+        shell: bash
+        if: ${{ env.GIT_DIFF || (github.event_name == 'pull_request' && github.ref == 'refs/heads/master') }}
+        run: |
+          ${PYTHON_EXEC} -m pip install -r requirements.txt
+          cat ${{ matrix.config.name }}_PNR/${{ matrix.config.name }}_task/config/task_simulation.conf
+          cd ${{ matrix.config.name }}_PNR && make clean runOpenFPGA
+      - name: Upload artifact
+        uses: actions/upload-artifact@v2
+        if: ${{ failure() }}
+        with:
+          name: failed_${{matrix.config.name}}_regression_log
+          retention-days: 1
+          path: "${{ matrix.config.name }}_PNR/*_task/latest/*.log"

.github/workflows/perform_precheck.sh

@@ -8,6 +8,13 @@ cd ./${DEST_DIR}
 echo "[Info] Running in directory ${PWD}"
 
 cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/
+if test -f "./gds/fpga_top_icv_in_design.gds.gz.sha1"; then
+    sha1sum --status -c ./gds/fpga_top_icv_in_design.gds.gz.sha1
+    status=$?
+    [ $status -eq 0 ] && echo "SHA1 matched GDS is already merged ... skipping drc" && exit
+fi
+fpga_top_sha1=$(sha1sum ./gds/fpga_top_icv_in_design.gds.gz)
+
 make uncompress
 echo "[Info] All files are uncompressed"
 
@@ -80,3 +87,4 @@ if [[ 0 -eq $(git cat-file -e $CARAVEL_COMPARE_COMMIT) ]]; then
     /usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt
     echo "[Info] Create compare_caravel.txt"
 fi
+echo $fpga_top_sha1 > ./gds/fpga_top_icv_in_design.gds.gz.sha1

.gitignore

@@ -11,3 +11,4 @@
 **/SRC**/*_tb.v
 **/SDC/**/*.sdc
 !**/SDC/**/disable_configure_ports.sdc
+*/runOpenFPGA

ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml

@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.61e-9
+L2_SB_MUX_DELAY: 1.61e-9
+L4_SB_MUX_DELAY: 1.61e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 0.86e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
+LUT4_DELAY: 1.14e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
+REGIN_TO_FF0_DELAY: 0.58e-9
+FF0_TO_FF1_DELAY: 0.56e-9

ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml

@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 0.81e-9
+L2_SB_MUX_DELAY: 0.81e-9
+L4_SB_MUX_DELAY: 0.81e-9
+CB_MUX_DELAY: 0.57e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 0.32e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.16e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.65e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.48e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.47e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.37e-9
+LUT3_DELAY: 0.86e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 0.65e-9
+LUT4_DELAY: 1.20e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 0.66e-9
+REGIN_TO_FF0_DELAY: 0.15e-9
+FF0_TO_FF1_DELAY: 0.16e-9

ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml

@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.44e-9
+L2_SB_MUX_DELAY: 1.44e-9
+L4_SB_MUX_DELAY: 1.44e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 0.92e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
+LUT4_DELAY: 1.21e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
+REGIN_TO_FF0_DELAY: 1.12e-9
+FF0_TO_FF1_DELAY: 0.56e-9