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[llvm][test] Fix filecheck annotation typos [1.5/n] #94857

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[llvm][test] Fix filecheck annotation typos [1.5/n] #94857

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d2a522d
working tests from #93673
Jun 8, 2024
e6b8c56
bless llvm/test/TableGen/MixedCasedMnemonic.td
Feb 3, 2025
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2 changes: 1 addition & 1 deletion llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll
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Expand Up @@ -31,7 +31,7 @@ define void @broadcast() #0{
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void

%zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/Assembler/bfloat.ll
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Expand Up @@ -37,25 +37,25 @@ define float @check_bfloat_convert() {
ret float %tmp
}

; ASSEM-DISASS-LABEL @snan_bfloat
; ASSEM-DISASS-LABEL: @snan_bfloat
define bfloat @snan_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7F81
ret bfloat 0xR7F81
}

; ASSEM-DISASS-LABEL @qnan_bfloat
; ASSEM-DISASS-LABEL: @qnan_bfloat
define bfloat @qnan_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7FC0
ret bfloat 0xR7FC0
}

; ASSEM-DISASS-LABEL @pos_inf_bfloat
; ASSEM-DISASS-LABEL: @pos_inf_bfloat
define bfloat @pos_inf_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7F80
ret bfloat 0xR7F80
}

; ASSEM-DISASS-LABEL @neg_inf_bfloat
; ASSEM-DISASS-LABEL: @neg_inf_bfloat
define bfloat @neg_inf_bfloat() {
; ASSEM-DISASS: ret bfloat 0xRFF80
ret bfloat 0xRFF80
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
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Expand Up @@ -2,70 +2,70 @@
; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS

define i8 @test_load_8(ptr %addr) {
; CHECK-LABAL: test_load_8:
; CHECK-LABEL: test_load_8:
; CHECK: ldarb w0, [x0]
%val = load atomic i8, ptr %addr seq_cst, align 1
ret i8 %val
}

define i16 @test_load_16(ptr %addr) {
; CHECK-LABAL: test_load_16:
; CHECK-LABEL: test_load_16:
; CHECK: ldarh w0, [x0]
%val = load atomic i16, ptr %addr acquire, align 2
ret i16 %val
}

define i32 @test_load_32(ptr %addr) {
; CHECK-LABAL: test_load_32:
; CHECK-LABEL: test_load_32:
; CHECK: ldar w0, [x0]
%val = load atomic i32, ptr %addr seq_cst, align 4
ret i32 %val
}

define i64 @test_load_64(ptr %addr) {
; CHECK-LABAL: test_load_64:
; CHECK-LABEL: test_load_64:
; CHECK: ldar x0, [x0]
%val = load atomic i64, ptr %addr seq_cst, align 8
ret i64 %val
}

define ptr @test_load_ptr(ptr %addr) {
; CHECK-LABAL: test_load_ptr:
; CHECK-LABEL: test_load_ptr:
; CHECK: ldar w0, [x0]
%val = load atomic ptr, ptr %addr seq_cst, align 8
ret ptr %val
}

define void @test_store_8(ptr %addr) {
; CHECK-LABAL: test_store_8:
; CHECK-LABEL: test_store_8:
; CHECK: stlrb wzr, [x0]
store atomic i8 0, ptr %addr seq_cst, align 1
ret void
}

define void @test_store_16(ptr %addr) {
; CHECK-LABAL: test_store_16:
; CHECK-LABEL: test_store_16:
; CHECK: stlrh wzr, [x0]
store atomic i16 0, ptr %addr seq_cst, align 2
ret void
}

define void @test_store_32(ptr %addr) {
; CHECK-LABAL: test_store_32:
; CHECK-LABEL: test_store_32:
; CHECK: stlr wzr, [x0]
store atomic i32 0, ptr %addr seq_cst, align 4
ret void
}

define void @test_store_64(ptr %addr) {
; CHECK-LABAL: test_store_64:
; CHECK-LABEL: test_store_64:
; CHECK: stlr xzr, [x0]
store atomic i64 0, ptr %addr seq_cst, align 8
ret void
}

define void @test_store_ptr(ptr %addr) {
; CHECK-LABAL: test_store_ptr:
; CHECK-LABEL: test_store_ptr:
; CHECK: stlr wzr, [x0]
store atomic ptr null, ptr %addr seq_cst, align 8
ret void
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
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@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s

define void @no_op() nounwind {
; CHECK-LABEL .def $ientry_thunk$cdecl$v$v;
; CHECK-LABEL: .def $ientry_thunk$cdecl$v$v;
; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$v$v
; CHECK: // %bb.0:
; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/fpimm.ll
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Expand Up @@ -38,7 +38,7 @@ define void @check_double() {
; 64-bit ORR followed by MOVK.
; CHECK-DAG: mov [[XFP0:x[0-9]+]], #1082331758844
; CHECK-DAG: movk [[XFP0]], #64764, lsl #16
; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]]
; CHECK-DAG: fmov {{d[0-9]+}}, [[XFP0]]
%newval3 = fadd double %val, 0xFCFCFC00FC
store volatile double %newval3, ptr @varf64

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
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Expand Up @@ -192,7 +192,7 @@ entry:
; CHECK: .Lfunc_end
}

; HARDEN-label: __llvm_slsblr_thunk_x0:
; HARDEN-LABEL: __llvm_slsblr_thunk_x0:
; HARDEN: mov x16, x0
; HARDEN: br x16
; ISBDSB-NEXT: dsb sy
Expand All @@ -208,7 +208,7 @@ entry:
; HARDEN-COMDAT-OFF-NOT: .hidden __llvm_slsblr_thunk_x19
; HARDEN-COMDAT-OFF-NOT: .weak __llvm_slsblr_thunk_x19
; HARDEN-COMDAT-OFF: .type __llvm_slsblr_thunk_x19,@function
; HARDEN-label: __llvm_slsblr_thunk_x19:
; HARDEN-LABEL: __llvm_slsblr_thunk_x19:
; HARDEN: mov x16, x19
; HARDEN: br x16
; ISBDSB-NEXT: dsb sy
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
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Expand Up @@ -12,7 +12,7 @@

# This test also checks that pairwise store STP is generated.

# CHECK-LABLE: test
# CHECK-LABEL: test
# CHECK: bb.0:
# CHECK-NEXT: liveins: $x0, $x17, $x18
# CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
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Expand Up @@ -22,7 +22,7 @@
; CHECK-DEFAULT: ldr{{.*}}, #4]
; CHECK-DEFAULT: str{{.*}}, #4]
; CHECK-DEFAULT: ldr{{.*}}, #8]!
; CHECK-DEAFULT: ldr{{.*}}, #8]!
; CHECK-DEFAULT: ldr{{.*}}, #8]!
; CHECK-DEFAULT: str{{.*}}, #8]!

; CHECK-COMPLEX: ldr{{.*}}, #8]!
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/ARM/shifter_operand.ll
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Expand Up @@ -121,7 +121,6 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) {
; CHECK-THUMB-NEXT: orrs r0, r1
; CHECK-THUMB-NEXT: bx lr
entry:
; CHECk-THUMB: orrs r0, r1
%mul = mul i32 %y, 63767
%or = or i32 %mul, %x
ret i32 %or
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
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Expand Up @@ -248,7 +248,7 @@ entry:
; HARDEN-COMDAT-OFF-NOT: .hidden {{__llvm_slsblr_thunk_(arm|thumb)_r5}}
; HARDEN-COMDAT-OFF-NOT: .weak {{__llvm_slsblr_thunk_(arm|thumb)_r5}}
; HARDEN-COMDAT-OFF: .type {{__llvm_slsblr_thunk_(arm|thumb)_r5}},%function
; HARDEN-label: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
; HARDEN-LABEL: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
; HARDEN: bx r5
; ISBDSB-NEXT: dsb sy
; ISBDSB-NEXT: isb
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/ARM/sxt_rot.ll
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Expand Up @@ -22,7 +22,6 @@ define signext i8 @test1(i32 %A) {
; CHECK-V7: @ %bb.0:
; CHECK-V7-NEXT: sbfx r0, r0, #8, #8
; CHECK-V7-NEXT: bx lr
; CHECk-V7: sbfx r0, r0, #8, #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
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Expand Up @@ -3,11 +3,11 @@
; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64

define i32 @shl_32(i32 %a, i32 %b) {
; MIPS32-LABLE: shl_32:
; MIPS32-LABEL: shl_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: sllv $2, $4, $5
; MIPS64-LABLE: shl_32:
; MIPS64-LABEL: shl_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
Expand All @@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) {
}

define i32 @lshr_32(i32 %a, i32 %b) {
; MIPS32-LABLE: lshr_32:
; MIPS32-LABEL: lshr_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srlv $2, $4, $5
; MIPS64-LABLE: lshr_32:
; MIPS64-LABEL: lshr_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
Expand All @@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) {
}

define i32 @ashr_32(i32 %a, i32 %b) {
; MIPS32-LABLE: ashr_32:
; MIPS32-LABEL: ashr_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srav $2, $4, $5
; MIPS64-LABLE: ashr_32:
; MIPS64-LABEL: ashr_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
Expand All @@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) {
}

define i64 @shl_64(i64 %a, i64 %b) {
; MIPS64-LABLE: shl_64:
; MIPS64-LABEL: shl_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
Expand All @@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) {
}

define i64 @lshr_64(i64 %a, i64 %b) {
; MIPS64-LABLE: lshr_64:
; MIPS64-LABEL: lshr_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
Expand All @@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) {
}

define i64 @ashr_64(i64 %a, i64 %b) {
; MIPS64-LABLE: ashr_64:
; MIPS64-LABEL: ashr_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/NVPTX/idioms.ll
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Expand Up @@ -42,7 +42,7 @@ define %struct.S16 @i32_to_2xi16(i32 noundef %in) {
%high = trunc i32 %high32 to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_param_0];
; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]];
; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
%s1 = insertvalue %struct.S16 poison, i16 %low, 0
%s = insertvalue %struct.S16 %s1, i16 %high, 1
ret %struct.S16 %s
Expand All @@ -56,7 +56,7 @@ define %struct.S16 @i32_to_2xi16_lh(i32 noundef %in) {
%low = trunc i32 %in to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_lh_param_0];
; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]];
; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
%s1 = insertvalue %struct.S16 poison, i16 %low, 0
%s = insertvalue %struct.S16 %s1, i16 %high, 1
ret %struct.S16 %s
Expand Down Expand Up @@ -84,7 +84,7 @@ define %struct.S32 @i64_to_2xi32(i64 noundef %in) {
%high = trunc i64 %high64 to i32
; CHECK: ld.param.u64 %[[R64:rd[0-9]+]], [i64_to_2xi32_param_0];
; CHECK-DAG: cvt.u32.u64 %r{{[0-9+]}}, %[[R64]];
; CHECK-DAG mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]];
; CHECK-DAG: mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]];
%s1 = insertvalue %struct.S32 poison, i32 %low, 0
%s = insertvalue %struct.S32 %s1, i32 %high, 1
ret %struct.S32 %s
Expand Down Expand Up @@ -114,8 +114,8 @@ define %struct.S16 @i32_to_2xi16_shr(i32 noundef %i){
%h = trunc i32 %h32 to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_shr_param_0];
; CHECK: shr.s32 %[[R32H:r[0-9]+]], %[[R32]], 16;
; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]];
; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]];
%s0 = insertvalue %struct.S16 poison, i16 %l, 0
%s1 = insertvalue %struct.S16 %s0, i16 %h, 1
ret %struct.S16 %s1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
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Expand Up @@ -7,7 +7,7 @@
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}

; CHECK-: Capability USMStorageClassesINTEL
; CHECK-SPIRV-WITHOUT-NO: Capability USMStorageClassesINTEL
; CHECK-SPIRV-WITHOUT-NOT: Capability USMStorageClassesINTEL
; CHECK-SPIRV-EXT-DAG: %[[DevTy:[0-9]+]] = OpTypePointer DeviceOnlyINTEL %[[#]]
; CHECK-SPIRV-EXT-DAG: %[[HostTy:[0-9]+]] = OpTypePointer HostOnlyINTEL %[[#]]
; CHECK-SPIRV-DAG: %[[CrsWrkTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[#]]
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/SystemZ/prefetch-04.ll
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Expand Up @@ -6,7 +6,7 @@
;
; CHECK-LABEL: for.body
; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1
; CHECK-not: call void @llvm.prefetch
; CHECK-NOT: call void @llvm.prefetch

define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) {
entry:
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
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Expand Up @@ -406,7 +406,7 @@ for.cond.cleanup:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
; CHECk-MID: tB %bb.2
; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_xor_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
Expand Down Expand Up @@ -440,7 +440,7 @@ while.end:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
; CHECk-MID: tB %bb.2
; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_cmp_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
Expand Down Expand Up @@ -474,7 +474,7 @@ while.end:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
; CHECk-MID: tB %bb.2
; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_reordered_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/global-sections.ll
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Expand Up @@ -35,9 +35,9 @@ bb5:
ret void
}

; LINUX: .size F2,
; LINUX-NEX: .cfi_endproc
; LINUX-NEX: .section .rodata,"a",@progbits
; LINUX: .size F2,
; LINUX-NEXT: .cfi_endproc
; LINUX-NEXT: .section .rodata,"a",@progbits

; LINUX-SECTIONS: .section .text.F2,"ax",@progbits
; LINUX-SECTIONS: .size F2,
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/tailregccpic.ll
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Expand Up @@ -13,12 +13,12 @@ entry:
ret void
}

;CHECK-LABLE: tail_call_regcall:
;CHECK-LABEL: tail_call_regcall:
;CHECK: # %bb.0:
;CHECK-NEXT: jmp __regcall3__func # TAILCALL
;CHECK-NEXT: .Lfunc_end0:

;CHECK-LABLE: __regcall3__func:
;CHECK-LABEL: __regcall3__func:
;CHECK: addl $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx
;CHECK-NEXT: movl a0@GOT(%ecx), %ecx
;CHECK-NEXT: movl %eax, (%ecx)
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
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Expand Up @@ -43,7 +43,7 @@ debugValueSubstitutions:
body: |
bb.0.entry:
successors: %bb.1, %bb.2
; CHECK-LABE: bb.0.entry:
; CHECK-LABEL: bb.0.entry:

$rax = MOV64ri 1, debug-instr-number 1, debug-location !17
DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17
Expand All @@ -69,8 +69,8 @@ body: |
;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17
;DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !17
;;; Test non-def operand
;; check: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
;; check-next: DBG_VALUE_LIST {{.+}}, $noreg
; COM: CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
; COM: CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg

$noreg = MOV32ri 1, debug-instr-number 5, debug-location !17
DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17
Expand Down
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