[RISCV] Set the isMoveReg flag for FMV_X_W

[sunshaoce]

It seems that other mv instructions should do this, but llvm's tests have not changed.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Shao-Ce SUN (sunshaoce)

Changes

It seems that other mv instructions should do this, but llvm's tests have not changed.

---

Full diff: https://github.com/llvm/llvm-project/pull/109378.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoF.td (+2-2)
• (modified) llvm/test/CodeGen/RISCV/select-const.ll (-4)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index a00acb372dc2a2..4bafd5c86c12c3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -388,11 +388,11 @@ foreach Ext = FExts in {
 } // foreach Ext = FExts
 
 let Predicates = [HasStdExtF], mayRaiseFPException = 0,
-    IsSignExtendingOpW = 1 in
+    IsSignExtendingOpW = 1, isMoveReg = 1 in
 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">,
               Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
 
-let Predicates = [HasStdExtF], mayRaiseFPException = 0 in
+let Predicates = [HasStdExtF], mayRaiseFPException = 0, isMoveReg = 1 in
 def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
               Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
 
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index 792df6236ddc0e..a8716e6afb80c3 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -102,8 +102,6 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
 ; RV32IF-NEXT:  .LBB4_2:
 ; RV32IF-NEXT:    lui a0, 263168
 ; RV32IF-NEXT:  .LBB4_3:
-; RV32IF-NEXT:    fmv.w.x fa5, a0
-; RV32IF-NEXT:    fmv.x.w a0, fa5
 ; RV32IF-NEXT:    ret
 ;
 ; RV64I-LABEL: select_const_fp:
@@ -125,8 +123,6 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
 ; RV64IFD-NEXT:  .LBB4_2:
 ; RV64IFD-NEXT:    lui a0, 263168
 ; RV64IFD-NEXT:  .LBB4_3:
-; RV64IFD-NEXT:    fmv.w.x fa5, a0
-; RV64IFD-NEXT:    fmv.x.w a0, fa5
 ; RV64IFD-NEXT:    ret
   %1 = select i1 %a, float 3.0, float 4.0
   ret float %1

[topperc]

llvm's tests have not changed.

There are test changes in this patch?

[topperc]

Only FMV_X_W is mentioned in the patch title

[dtcxzyw]

IIRC isMoveReg only applies to copies within the same register class or reg <-> subreg copies. Have you seen other targets set this flag for fp <-> int moves?

[topperc]

I'm not sure what all isMoveReg is used for. On RV64, this instruction has sign extending behavior. It might not be safe to do generic optimizations with it.

[sunshaoce]

I searched for x86 and Arm, and it is true that there are only examples of use between registers of the same kind. Also, as @topperc said, this is not safe and I will close this PR. Thank you all for your comments!