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[CIR][CIRGen][Builtin][Neon] Lower neon_vset_lane_f64 #1253

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10 changes: 7 additions & 3 deletions clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3687,9 +3687,13 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
// at the moment, the implementation should be the same as above
// vset_lane or vsetq_lane intrinsics
llvm_unreachable("NEON::BI__builtin_neon_vsetq_lane_bf16 NYI");
case NEON::BI__builtin_neon_vset_lane_f64:
// The vector type needs a cast for the v1f64 variant.
llvm_unreachable("NEON::BI__builtin_neon_vset_lane_f64 NYI");
case NEON::BI__builtin_neon_vset_lane_f64: {
Ops.push_back(emitScalarExpr(E->getArg(2)));
Ops[1] = builder.createBitcast(
Ops[1], cir::VectorType::get(&getMLIRContext(), DoubleTy, 1));
return builder.create<cir::VecInsertOp>(getLoc(E->getExprLoc()), Ops[1],
Ops[0], Ops[2]);
}
case NEON::BI__builtin_neon_vsetq_lane_f64:
// The vector type needs a cast for the v2f64 variant.
llvm_unreachable("NEON::BI__builtin_neon_vsetq_lane_f64 NYI");
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12 changes: 12 additions & 0 deletions clang/test/CIR/CodeGen/AArch64/neon-misc.c
Original file line number Diff line number Diff line change
Expand Up @@ -137,6 +137,18 @@ float32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) {
// LLVM: [[INTRN_RES:%.*]] = insertelement <4 x float> [[B]], float [[A]], i32 3
// LLVM: ret <4 x float> [[INTRN_RES]]

float64x1_t test_vset_lane_f64(float64_t a, float64x1_t b) {
return vset_lane_f64(a, b, 0);
}

// CIR-LABEL: test_vset_lane_f64
// CIR: [[IDX:%.*]] = cir.const #cir.int<0> : !s32i
// CIR: {{%.*}} = cir.vec.insert {{%.*}}, {{%.*}}[[[IDX]] : !s32i] : !cir.vector<!cir.double x 1>

// LLVM: {{.*}}test_vset_lane_f64(double{{.*}}[[A:%.*]], <1 x double>{{.*}}[[B:%.*]])
// LLVM: [[INTRN_RES:%.*]] = insertelement <1 x double> [[B]], double [[A]], i32 0
// LLVM: ret <1 x double> [[INTRN_RES]]

uint8_t test_vget_lane_u8(uint8x8_t a) {
return vget_lane_u8(a, 7);
}
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