GAL source and programming file

linker3000 · Jul 29, 2020 · 67a21e1 · 67a21e1
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diff --git a/specrom.jed b/specrom.jed
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+CUPL(WM)        5.0a  Serial# 60008009
+Device          g22v10  Library DLIB-h-40-1
+Created         Mon Jul 27 22:53:25 2020
+Name            specrom
+Partno          XXXXX
+Revision        01
+Date            19-Jul-2020
+Designer        N. Kendrick
+Company         Techmarque
+Assembly        XXXXX
+Location        XXXXX
+*QP24 
+*QF5892 
+*QV48
+*G0 
+*F0 
+*L00032 00000000000011111111111111111111
+*L00064 11111111111111111111111111111111
+*L00096 11111111111110111001111011101110
+*L00128 10100000000000000000000000000000
+*L00416 00000000000000000000000011111111
+*L00448 11111111111111111111111111111111
+*L00480 11111111111111111111111110111010
+*L00512 11011101110101010000000000000000
+*L01472 00000000000000000000000011111111
+*L01504 11111111111111111111111111111111
+*L01536 11111011011111111111111111111111
+*L01568 11111111111111111111111111111111
+*L01600 11111111111111110111111111111111
+*L01632 10111111111111111111111101111111
+*L01664 11111111111111110111111111111111
+*L01696 11111111111111111111111111111111
+*L01728 10111111111111111111111111111111
+*L01760 11111111110111111111111111111111
+*L01792 11111111111111111111111111111111
+*L01824 11111111111111110111111100000000
+*L02144 00000000000011111111111111111111
+*L02176 11111111111111111111111110111111
+*L02208 11111011111111111111111111111111
+*L02240 11111111111111111111111111111111
+*L02272 11110111111111111111111111111111
+*L02304 11111111111101111111111111111011
+*L02336 10111111111111111111111111111111
+*L02368 11111111111111111011101111111111
+*L02400 11111111111111111111111110111111
+*L02432 10111111111111111111111111111111
+*L02464 11111111110111111111111111111111
+*L02496 11111111111111111111111111111111
+*L02528 11111111111111110111111100000000
+*L02880 00000000000000000000000011111111
+*L02912 11111111111111111111111111111111
+*L02944 11111011101111100111111111111111
+*L02976 01111011101111110111101110100111
+*L03008 11111111111101111011101111111111
+*L03040 11111111111111111111111111110111
+*L03072 11111111111111111111101111111111
+*L03104 11110111111111111111011111110111
+*L03136 11111111111111110111111111111111
+*L03168 11111111101110111111111111111111
+*L03200 11111111111111111011111110111111
+*L03232 11111111111111111111111111111111
+*L03264 11011111111111111111111111111111
+*L03296 11111111111111111111111111111111
+*L03328 11111111011111110000000000000000
+*L05792 00000000000000000101011111110101
+*L05824 01010101100001011000010110000101
+*L05856 10000101100000000000000000000000
+*CAA21
+*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
+*V0001 0111XXX000XNXXXXXLLH0XXN
+*V0002 0111XXX100XNXXXXXLHH0XXN
+*V0003 0111XXX010XNXXXXXHHH0XXN
+*V0004 0111XXX110XNXXXXXHHH0XXN
+*V0005 0111XXX001XNXXXXXHHH0XXN
+*V0006 0111XXX101XNXXXXXHHH0XXN
+*V0007 0111XXX011XNXXXXXHHH0XXN
+*V0008 0111XXX111XNXXXXXHHH0XXN
+*V0009 0111XXX000XNXXXXXHHH1XXN
+*V0010 0111XXX100XNXXXXXHHH1XXN
+*V0011 0111XXX010XNXXXXXHHH1XXN
+*V0012 0111XXX110XNXXXXXHHH1XXN
+*V0013 0111XXX001XNXXXXXHHH1XXN
+*V0014 0111XXX101XNXXXXXHHH1XXN
+*V0015 0111XXX011XNXXXXXHHH1XXN
+*V0016 0111XXX111XNXXXXXHHH1XXN
+*V0017 1101XXX000XNXXXXXLLL0XXN
+*V0018 1101XXX100XNXXXXXLHL0XXN
+*V0019 1101XXX010XNXXXXXHHH0XXN
+*V0020 1101XXX110XNXXXXXHHH0XXN
+*V0021 1101XXX001XNXXXXXHHH0XXN
+*V0022 1101XXX101XNXXXXXHHH0XXN
+*V0023 1101XXX011XNXXXXXHHH0XXN
+*V0024 1101XXX111XNXXXXXHHH0XXN
+*V0025 1101XXX000XNXXXXXHHH1XXN
+*V0026 1101XXX100XNXXXXXHHH1XXN
+*V0027 1101XXX010XNXXXXXHHH1XXN
+*V0028 1101XXX110XNXXXXXHHH1XXN
+*V0029 1101XXX001XNXXXXXHHH1XXN
+*V0030 1101XXX101XNXXXXXHHH1XXN
+*V0031 1101XXX011XNXXXXXHHH1XXN
+*V0032 0101XXX111XNXXXXXHHH1XXN
+*V0033 0101XXX000XNXXXXXLLH0XXN
+*V0034 0101XXX100XNXXXXXLHH0XXN
+*V0035 0101XXX010XNXXXXXHHH0XXN
+*V0036 0101XXX110XNXXXXXHHH0XXN
+*V0037 0101XXX001XNXXXXXHHH0XXN
+*V0038 0101XXX101XNXXXXXHHH0XXN
+*V0039 0101XXX011XNXXXXXHHH0XXN
+*V0040 0101XXX111XNXXXXXHHH0XXN
+*V0041 0101XXX000XNXXXXXHHH1XXN
+*V0042 0101XXX100XNXXXXXHHH1XXN
+*V0043 0101XXX010XNXXXXXHHH1XXN
+*V0044 0101XXX110XNXXXXXHHH1XXN
+*V0045 0101XXX001XNXXXXXHHH1XXN
+*V0046 0101XXX101XNXXXXXHHH1XXN
+*V0047 0101XXX011XNXXXXXHHH1XXN
+*V0048 1101XXX111XNXXXXXHHH1XXN
+*7B27
diff --git a/specrom.pld b/specrom.pld
@@ -0,0 +1 @@
+Name       specrom;Partno     XXXXX;Date       19-Jul-2020;Revision   01;Designer   N. Kendrick;Company    Techmarque;Assembly   XXXXX;Location   XXXXX;Device     g22v10;/*************************************************************** Licence: CC BY-NC-SA V3  Not for commercial use.           N. Kendrick 2020  This Code does ROM/size select for a ZX Spectrum ROM board using a   4-bit BCD rotary PCB switch.         Switch options are:                                             0 = 8K in 2764                                                      1 = 16K in 27128                                                    2 = 8K in 1st half of 27128                                         3 = 8K in 2nd half of 27128                                         4 = 16K in 1st half of 27256                                                 5 = 16K in 2nd half of 27256                                                 6 = 8K in 1st quarter of 27256                                              7 = 8K in 2nd quarter of 27256                                              8 = 8K in 3rd quarter of 27256                                              9 = 8K in 4th quarter of 27256                                             Switch line inputs on GAL should have pullups, and the switch   will ground the relevant binary lines to indicate a number, so  4-bit logic for switch values is reversed - e.g. 0 = 1111       ROMCE controls 'Chip Enable' on the ROM and should be LO for the ROM  to be accesses.  A PNP transistor circuit* is typically used to simultaneously pull  ROMCS on the Spectrum bus high to disable its internal ROM while  presenting LO to ROMCE on the GAL. 'Output Enable' on the ROM is controlled by /MREQ from the spectrum  bus. Bonus feature, JOY_ENx are active low outputs for controlling a dual Kempston-type joystick interface based on two LS240 chips*. *See: https://github.com/linker3000 for more details.*************************** SPECROM ****************************                 ______________                |   SPECROM    |          SWA---|1  I        24|---Vcc          SWB---|2  I      O 23|---JOY_EN2           SWC---|3  I      O 22|---JOY_EN1           SWD---|4  I      I 21|---ROMEN           NC---|5  X      O 20|---A14_ROM     IORQ_BUS---|6  I      O 19|---A13_ROM        RD_BUS---|7  I      O 18|---ROMCE (To ROM)      A13_BUS---|8  I      I 17|---A5_BUS      A14_BUS---|9  I      I 16|---A4_BUS      A15_BUS---|10 I      I 15|---A3_BUS        A0_BUS---|11 I      I 14|---A2_BUS           GND---|12        I 13|---A1_BUS                 |____22V10_____|*****************************************************************//**  Inputs  **//* From local circuitry */Pin 1  = SWA;   /* BCD switch pins - active low, so 0 = 1111 */Pin 2  = SWB;   Pin 3  = SWC;   Pin 4  = SWD; Pin 21 = ROMEN; /* LO = ROM enabled by jumper *//* From Spectrum edge connector */Pin 6  = IORQ_BUS; /* /IORQ Spectrum bus for joystick reads */Pin 7  = RD_BUS;   /* /RD_Bus Spectrum bus - read cycle indicator */Pin 8  = A13_BUS;  /* A13 Spectrum bus */Pin 9  = A14_BUS;  /* A14 Spectrum bus */Pin 10 = A15_BUS;  /* A15 Spectrum bus HI = Not ROM access */Pin 11 = A0_BUS;   /* ZX Spectrum address bus A0-A5 */Pin 13 = A1_BUS;Pin 14 = A2_BUS;Pin 15 = A3_BUS;Pin 16 = A4_BUS;Pin 17 = A5_BUS;/**  Outputs  **/Pin 18 = ROMCE;   /* LO = ROM chip enable. Also connect to ~ROMCS on Spec. bus via transistor */Pin 19 = A13_ROM; /* A13 on ROM */Pin 20 = A14_ROM; /* A14 on 27x256 and ~PGM on 27x64/27x128 (Always set HI on these two chips */Pin 22 = !JOY_EN1; /* Joystick port enable pin JOY1 active LO = port $1F */Pin 23 = !JOY_EN2; /* Joystick port enable pin JOY2 active LO = port $20 *//**  Truth table setup and equations  **/FIELD INPUT  = [ROMEN, A15_BUS, A14_BUS, A13_BUS, SWD, SWC, SWB, SWA];  /* Defines input array    */FIELD OUTPUT = [ROMCE, A14_ROM, A13_ROM];  /* Defines output array */TABLE INPUT => OUTPUT {/* ROM size and location in chip based on switch position... *//* Bits = ROMEN, A15, A14, A13, SWD, SWC, SWB, SWA => ROMCE A14_ROM A13_ROM  *//* But first, two conditions which need ROM to be disabled... *//* ROMEN is HI so ROM not enabled */'b'1XXXXXXX => 'b'111;  /* A15 is HI so not a ROM address */'b'X1XXXXXX => 'b'111; /* Mapping for 2764 8K chip... */'b'00001111 => 'b'010; /* 0 = 8K ROM: A14PGM always HI, A13 Not used */'b'00011111 => 'b'111; /* 0 = Not valid */'b'00101111 => 'b'111; /* 0 = Not valid */'b'00111111 => 'b'111; /* 0 = Not valid *//* Mappings for 27128 16K chip... */'b'00001110 => 'b'010; /* 1 = 16K ROM: 1st 8K. A14PGM always HI, A13 = 0 */'b'00011110 => 'b'011; /* 1 = 16K ROM: 2nd 8K. A14PGM always HI, A13 = 1 */'b'00101110 => 'b'111; /* 1 = Not valid */'b'00111110 => 'b'111; /* 1 = Not valid */'b'00001101 => 'b'010; /* 2 = 8K ROM in 1st half of chip. A14PGM always HI, A13 = 0 */'b'00011101 => 'b'111; /* 2 = Not valid */'b'00101101 => 'b'111; /* 2 = Not valid */'b'00111101 => 'b'111; /* 2 = Not valid */'b'00001100 => 'b'011; /* 3 = 8K ROM in 2nd half of chip. A14PGM always HI, A13 = 1 */'b'00011100 => 'b'111; /* 3 = Not valid */'b'00101100 => 'b'111; /* 3 = Not valid */'b'00111100 => 'b'111; /* 3 = Not valid *//* Mappings for 27256 32K chip... */'b'00001011 => 'b'000; /* 4 = 16K ROM: 1st half in 1st quarter of chip = A14 A13 = 00 */'b'00011011 => 'b'001; /* 4 = 16K ROM: 2nd half in 2nd quarter of chip = A14 A13 = 01 */'b'00101011 => 'b'111; /* 4 = Not valid */'b'00111011 => 'b'111; /* 4 = Not valid */'b'00001010 => 'b'010; /* 5 = 16K ROM: 1st half in 3rd quarter of chip = A14 A13 = 10 */'b'00011010 => 'b'011; /* 5 = 16K ROM: 2nd half in 4th quarter of chip = A14 A13 = 11 */'b'00101010 => 'b'111; /* 5 = Not valid */'b'00111010 => 'b'111; /* 5 = Not valid */'b'00001001 => 'b'000; /* 6 = 8K ROM in 1st quarter of chip = A14 A13 = 00 */'b'00011001 => 'b'111; /* 6 = Not valid */'b'00101001 => 'b'111; /* 6 = Not valid */'b'00111001 => 'b'111; /* 6 = Not valid */'b'00001000 => 'b'001; /* 7 = 8K ROM in 2nd quarter of chip = A14 A13 = 01 */'b'00011000 => 'b'111; /* 7 = Not valid */'b'00101000 => 'b'111; /* 7 = Not valid */'b'00111000 => 'b'111; /* 7 = Not valid */'b'00000111 => 'b'010; /* 8 = 8K ROM in 3rd quarter of chip = A14 A13 = 10  */'b'00010111 => 'b'111; /* 8 = Not valid */'b'00100111 => 'b'111; /* 8 = Not valid */'b'00110111 => 'b'111; /* 8 = Not valid */'b'00000110 => 'b'011; /* 9 = 8K ROM in 4th quarter of chip = A14 A13 = 11  */'b'00010110 => 'b'111; /* 9 = Not valid */'b'00100110 => 'b'111; /* 9 = Not valid */'b'00110110 => 'b'111; /* 9 = Not valid *//* Invalid BCD switch positions - Should not occur unless hex switch used...*//* In any case, disable ROM for these switch values */'b'XXXX0101 => 'b'111; /* A (10) */'b'XXXX0100 => 'b'111; /* B (11) */'b'XXXX0011 => 'b'111; /* C (12) */'b'XXXX0010 => 'b'111; /* D (13) */'b'XXXX0001 => 'b'111; /* E (14) */'b'XXXX0000 => 'b'111; /* F (15) */}/* Joystick interfaces enable on ports $1F and $20 */JOY_EN1 = !IORQ_BUS & !RD_BUS & !A5_BUS &  A4_BUS &  A3_BUS &  A2_BUS &  A1_BUS &  A0_BUS; JOY_EN2 = !IORQ_BUS & !RD_BUS &  A5_BUS & !A4_BUS & !A3_BUS & !A2_BUS & !A1_BUS & !A0_BUS;
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		Name specrom;Partno XXXXX;Date 19-Jul-2020;Revision 01;Designer N. Kendrick;Company Techmarque;Assembly XXXXX;Location XXXXX;Device g22v10;/*************************************************************** Licence: CC BY-NC-SA V3 Not for commercial use. N. Kendrick 2020 This Code does ROM/size select for a ZX Spectrum ROM board using a 4-bit BCD rotary PCB switch. Switch options are: 0 = 8K in 2764 1 = 16K in 27128 2 = 8K in 1st half of 27128 3 = 8K in 2nd half of 27128 4 = 16K in 1st half of 27256 5 = 16K in 2nd half of 27256 6 = 8K in 1st quarter of 27256 7 = 8K in 2nd quarter of 27256 8 = 8K in 3rd quarter of 27256 9 = 8K in 4th quarter of 27256 Switch line inputs on GAL should have pullups, and the switch will ground the relevant binary lines to indicate a number, so 4-bit logic for switch values is reversed - e.g. 0 = 1111 ROMCE controls 'Chip Enable' on the ROM and should be LO for the ROM to be accesses. A PNP transistor circuit* is typically used to simultaneously pull ROMCS on the Spectrum bus high to disable its internal ROM while presenting LO to ROMCE on the GAL. 'Output Enable' on the ROM is controlled by /MREQ from the spectrum bus. Bonus feature, JOY_ENx are active low outputs for controlling a dual Kempston-type joystick interface based on two LS240 chips. See: https://github.com/linker3000 for more details.************************* SPECROM ************************ ______________ \| SPECROM \| SWA---\|1 I 24\|---Vcc SWB---\|2 I O 23\|---JOY_EN2 SWC---\|3 I O 22\|---JOY_EN1 SWD---\|4 I I 21\|---ROMEN NC---\|5 X O 20\|---A14_ROM IORQ_BUS---\|6 I O 19\|---A13_ROM RD_BUS---\|7 I O 18\|---ROMCE (To ROM) A13_BUS---\|8 I I 17\|---A5_BUS A14_BUS---\|9 I I 16\|---A4_BUS A15_BUS---\|10 I I 15\|---A3_BUS A0_BUS---\|11 I I 14\|---A2_BUS GND---\|12 I 13\|---A1_BUS \|____22V10_____\|*************************************************************// Inputs *// From local circuitry /Pin 1 = SWA; / BCD switch pins - active low, so 0 = 1111 /Pin 2 = SWB; Pin 3 = SWC; Pin 4 = SWD; Pin 21 = ROMEN; / LO = ROM enabled by jumper // From Spectrum edge connector /Pin 6 = IORQ_BUS; / /IORQ Spectrum bus for joystick reads /Pin 7 = RD_BUS; / /RD_Bus Spectrum bus - read cycle indicator /Pin 8 = A13_BUS; / A13 Spectrum bus /Pin 9 = A14_BUS; / A14 Spectrum bus /Pin 10 = A15_BUS; / A15 Spectrum bus HI = Not ROM access /Pin 11 = A0_BUS; / ZX Spectrum address bus A0-A5 /Pin 13 = A1_BUS;Pin 14 = A2_BUS;Pin 15 = A3_BUS;Pin 16 = A4_BUS;Pin 17 = A5_BUS;/* Outputs */Pin 18 = ROMCE; / LO = ROM chip enable. Also connect to ~ROMCS on Spec. bus via transistor /Pin 19 = A13_ROM; / A13 on ROM /Pin 20 = A14_ROM; / A14 on 27x256 and ~PGM on 27x64/27x128 (Always set HI on these two chips /Pin 22 = !JOY_EN1; / Joystick port enable pin JOY1 active LO = port $1F /Pin 23 = !JOY_EN2; / Joystick port enable pin JOY2 active LO = port $20 //* Truth table setup and equations */FIELD INPUT = [ROMEN, A15_BUS, A14_BUS, A13_BUS, SWD, SWC, SWB, SWA]; / Defines input array /FIELD OUTPUT = [ROMCE, A14_ROM, A13_ROM]; / Defines output array /TABLE INPUT => OUTPUT {/ ROM size and location in chip based on switch position... // Bits = ROMEN, A15, A14, A13, SWD, SWC, SWB, SWA => ROMCE A14_ROM A13_ROM // But first, two conditions which need ROM to be disabled... // ROMEN is HI so ROM not enabled /'b'1XXXXXXX => 'b'111; / A15 is HI so not a ROM address /'b'X1XXXXXX => 'b'111; / Mapping for 2764 8K chip... /'b'00001111 => 'b'010; / 0 = 8K ROM: A14PGM always HI, A13 Not used /'b'00011111 => 'b'111; / 0 = Not valid /'b'00101111 => 'b'111; / 0 = Not valid /'b'00111111 => 'b'111; / 0 = Not valid // Mappings for 27128 16K chip... /'b'00001110 => 'b'010; / 1 = 16K ROM: 1st 8K. A14PGM always HI, A13 = 0 /'b'00011110 => 'b'011; / 1 = 16K ROM: 2nd 8K. A14PGM always HI, A13 = 1 /'b'00101110 => 'b'111; / 1 = Not valid /'b'00111110 => 'b'111; / 1 = Not valid /'b'00001101 => 'b'010; / 2 = 8K ROM in 1st half of chip. A14PGM always HI, A13 = 0 /'b'00011101 => 'b'111; / 2 = Not valid /'b'00101101 => 'b'111; / 2 = Not valid /'b'00111101 => 'b'111; / 2 = Not valid /'b'00001100 => 'b'011; / 3 = 8K ROM in 2nd half of chip. A14PGM always HI, A13 = 1 /'b'00011100 => 'b'111; / 3 = Not valid /'b'00101100 => 'b'111; / 3 = Not valid /'b'00111100 => 'b'111; / 3 = Not valid // Mappings for 27256 32K chip... /'b'00001011 => 'b'000; / 4 = 16K ROM: 1st half in 1st quarter of chip = A14 A13 = 00 /'b'00011011 => 'b'001; / 4 = 16K ROM: 2nd half in 2nd quarter of chip = A14 A13 = 01 /'b'00101011 => 'b'111; / 4 = Not valid /'b'00111011 => 'b'111; / 4 = Not valid /'b'00001010 => 'b'010; / 5 = 16K ROM: 1st half in 3rd quarter of chip = A14 A13 = 10 /'b'00011010 => 'b'011; / 5 = 16K ROM: 2nd half in 4th quarter of chip = A14 A13 = 11 /'b'00101010 => 'b'111; / 5 = Not valid /'b'00111010 => 'b'111; / 5 = Not valid /'b'00001001 => 'b'000; / 6 = 8K ROM in 1st quarter of chip = A14 A13 = 00 /'b'00011001 => 'b'111; / 6 = Not valid /'b'00101001 => 'b'111; / 6 = Not valid /'b'00111001 => 'b'111; / 6 = Not valid /'b'00001000 => 'b'001; / 7 = 8K ROM in 2nd quarter of chip = A14 A13 = 01 /'b'00011000 => 'b'111; / 7 = Not valid /'b'00101000 => 'b'111; / 7 = Not valid /'b'00111000 => 'b'111; / 7 = Not valid /'b'00000111 => 'b'010; / 8 = 8K ROM in 3rd quarter of chip = A14 A13 = 10 /'b'00010111 => 'b'111; / 8 = Not valid /'b'00100111 => 'b'111; / 8 = Not valid /'b'00110111 => 'b'111; / 8 = Not valid /'b'00000110 => 'b'011; / 9 = 8K ROM in 4th quarter of chip = A14 A13 = 11 /'b'00010110 => 'b'111; / 9 = Not valid /'b'00100110 => 'b'111; / 9 = Not valid /'b'00110110 => 'b'111; / 9 = Not valid // Invalid BCD switch positions - Should not occur unless hex switch used...// In any case, disable ROM for these switch values /'b'XXXX0101 => 'b'111; / A (10) /'b'XXXX0100 => 'b'111; / B (11) /'b'XXXX0011 => 'b'111; / C (12) /'b'XXXX0010 => 'b'111; / D (13) /'b'XXXX0001 => 'b'111; / E (14) /'b'XXXX0000 => 'b'111; / F (15) /}/ Joystick interfaces enable on ports $1F and $20 */JOY_EN1 = !IORQ_BUS & !RD_BUS & !A5_BUS & A4_BUS & A3_BUS & A2_BUS & A1_BUS & A0_BUS; JOY_EN2 = !IORQ_BUS & !RD_BUS & A5_BUS & !A4_BUS & !A3_BUS & !A2_BUS & !A1_BUS & !A0_BUS;
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