Merge pull request #23 from lf-lang/s4noc-maven

lf-lang · Jun 9, 2023 · 80a1ed3 · 80a1ed3
2 parents ab3f7a2 + ff52219
commit 80a1ed3
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Showing 8 changed files with 8 additions and 14 deletions.
diff --git a/.gitignore b/.gitignore
@@ -1,6 +1,7 @@
 .bsp/
 .metals/
 .vscode/
+.idea/
 project/
 target/
 build/

diff --git a/.gitmodules b/.gitmodules
@@ -1,6 +1,3 @@
 [submodule "flexpret"]
 	path = flexpret
 	url = https://github.com/pretis/flexpret.git
-[submodule "soc-comm"]
-	path = soc-comm
-	url = https://github.com/t-crest/soc-comm
diff --git a/README.md b/README.md
@@ -7,7 +7,7 @@ InterPRET is a multicore FlexPRET architecture that uses a time-predictable Netw
 ### Prerequisites
 1. Verilator
 2. SBT
-3. RISCV 32-bit toolchain
+3. RISCV toolchain on the PATH. Download prebuild [rv32i-4.0.0](https://github.com/stnolting/riscv-gcc-prebuilt)
 
 ### Clone repo and set up 
 ```

diff --git a/build.sbt b/build.sbt
@@ -8,6 +8,7 @@ lazy val interpret = (project in file("."))
     libraryDependencies ++= Seq(
       "edu.berkeley.cs" %% "chisel3" % chiselVersion,
       "edu.berkeley.cs" %% "chiseltest" % "0.5.5",
+      "io.github.t-crest" % "soc-comm" % "0.1.5"
     ),
 scalaVersion := "2.12.10", // Issue on scalamacros:paradise
 scalacOptions ++= Seq(
@@ -18,10 +19,7 @@ scalacOptions ++= Seq(
 ),
 addCompilerPlugin("edu.berkeley.cs" %% "chisel3-plugin" % chiselVersion cross CrossVersion.full),
 addCompilerPlugin("org.scalamacros" %% "paradise" % "2.1.0" cross CrossVersion.full)
-  ).dependsOn(flexpret,soc_comm)
+  ).dependsOn(flexpret)
 
 // Import flexpret
 lazy val flexpret = (project in file("./flexpret"))
-
-// Import soc-comm
-lazy val soc_comm = (project in file("./soc-comm"))
diff --git a/env.fish b/env.fish
@@ -1,6 +1,5 @@
 set -Ux FP_ROOT (pwd)
 
-set PATH $PATH:/opt/riscv32/bin
 set PATH $PATH:$FP_ROOT/flexpret/scripts/c
 set PATH $PATH:$FP_ROOT/emulator
 set PATH $PATH:$FP_ROOT/programs/scripts
diff --git a/programs/integration-tests.mk b/programs/integration-tests.mk
@@ -21,12 +21,12 @@ integration-tests: $(TEST_RESULTS) bootloader-test
 $(TEST_DIR)/%/test_res.txt: $(TEST_DIR)/%
 	@echo Executing $^
 	@cd $^; make rebuild
-	@cd $^; if ! (fp-emu > test_res.txt 2>&1); then continue; fi
+	@cd $^; if ! (ip-verilator > test_res.txt 2>&1); then continue; fi
 	@test_result_parse.sh $@
 
 bootloader-test:
 	@cd programs/bootloader; riscv-clean.sh; make; compile_app.sh 1 hello hello.c
-	@cd programs/bootloader; if ! (fp-emu hello.app > test_res.txt 2>&1); then continue; fi
+	@cd programs/bootloader; if ! (ip-verilator hello.app > test_res.txt 2>&1); then continue; fi
 	@cd programs/bootloader; test_result_parse.sh test_res.txt
 
 .PHONY: integration-clean

diff --git a/soc-comm b/soc-comm
diff --git a/src/main/scala/Top.scala b/src/main/scala/Top.scala
@@ -5,7 +5,7 @@ import chisel3.experimental.{annotate, ChiselAnnotation}
 import firrtl.annotations.MemorySynthInit
 import flexpret.core.{Core, FlexpretConfiguration, GPIO, HostIO, ISpm}
 
-import s4noc.{Config, S4NoCTop}
+import s4noc.{Config, S4NoCTop, RegType}
 
 
 case class TopConfig(
@@ -50,7 +50,7 @@ class Top(topCfg: TopConfig) extends Module {
   // Normally InterPRET requires 2x2, 3x3, 4x4 etc cores. But we also support the edge case of
   //  have a single core. We then make a NoC with 4 ports and just drive the remaining 3 to defaults
   val nNocPorts = if (topCfg.nCores == 1) 4 else topCfg.nCores
-  val noc = Module(new S4NoCTop(Config(nNocPorts, 2, 2, 2, 32)))
+  val noc = Module(new S4NoCTop(Config(nNocPorts, RegType(2), RegType(2), RegType(2), 32)))
 
   for (i <- 0 until nNocPorts) {
     noc.io.cpuPorts(i).wrData := 0.U