This milestone is for delivering the promised performance advantages of out-of-order processors. The most critical tasks are:

1. Improve fetching performance. Probably the best solution would be to introduce an instruction cache, which would communicate via Wishbone bus using bursting.
2. Implement a non-trivial load-store unit, which queues and reorders loads/stores to achieve higher performance.
3. Add speculative execution. We need to stop stalling at jump/branch instructions. At first, we can use the trivial strategy of "always predict not taken".
4. Add superscalar execution. This is factored out to another milestone, https://github.com/kuznia-rdzeni/coreblocks/milestone/8.
5. Measure core IPC (instructions per cycle) for various benchmark programs.