Bump Chisel 6.2.0 (OpenXiangShan#304)

klin02 · Mar 8, 2024 · be02e59 · be02e59
1 parent 666a1ec
commit be02e59
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diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
@@ -22,7 +22,7 @@ jobs:
       - name: Compile
         run: |
           mill -i design[3.6.0].compile
-          mill -i design[6.1.0].compile
+          mill -i design[6.2.0].compile
 
       - name: Generate Verilog
         run: |

diff --git a/build.sc b/build.sc
@@ -22,7 +22,7 @@ object ivys {
   val scala = "2.13.10"
   val chiselCrossVersions = Map(
     "3.6.0" -> (ivy"edu.berkeley.cs::chisel3:3.6.0", ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0"),
-    "6.1.0" -> (ivy"org.chipsalliance::chisel:6.1.0", ivy"org.chipsalliance:::chisel-plugin:6.1.0"),
+    "6.2.0" -> (ivy"org.chipsalliance::chisel:6.2.0", ivy"org.chipsalliance:::chisel-plugin:6.2.0"),
   )
 }