Added YM2203 support

README.md

@@ -1,2 +1,24 @@
 # jt12
-FM sound source written in Verilog, fully compatible with YM2612
+
+FM sound source written in Verilog, fully compatible with YM2612 and YM2203.
+
+The implementation tries to be as close to original hardware as possible. Low usage of FPGA resources has also been a design goal. Except in the operator section (jt12_op) where an exact replica of the original circuit is done. This could be done in less space with a different style but because this piece of the circuit was reversed engineered by Sauraen, I decided to use that knowledge.
+
+Directories:
+
+hdl -> all relevant RTL files, written in verilog
+ver -> test benches
+ver/verilator -> test bench that can play vgm files
+
+Usage:
+
+YM2612: top level file "jt12.v". Use jt12.qip to automatically get all relevant files in Quartus.
+    YM2612 should have parameters set like:
+        use_lfo = 1
+        use_psg = 0
+
+YM2203: top level file "jt12.v". Use jt03.qip to automatically get all relevant files in Quartus.
+    YM2203 should have parameters set like:
+        use_lfo = 0
+        use_psg = 1
+

hdl/jt03.qip

@@ -0,0 +1,36 @@
+set_global_assignment -name VHDL_FILE    [file join $::quartus(qip_path) jt12.vhd ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_acc.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_cnt.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_comb.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_step.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_pure.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_final.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_ctrl.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_exprom.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_kon.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_lfo.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_limitamp.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_mmr.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_mod.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_op.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_opram.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg_inc.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg_dt.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg_sum.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg_comb.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pm.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_phrom.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_reg.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh_rst.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh24.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sumch.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_timers.v ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../jt49/hdl/jt49.h ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../jt49/hdl/jt49_div.h ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../jt49/hdl/jt49_eg.h ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../jt49/hdl/jt49_exp.h ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../jt49/hdl/jt49_noise.h ]

hdl/jt12.v

@@ -315,7 +315,8 @@ jt12_sh #(.width(10),.stages(4)) u_egpad(
     .drop   ( eg_IX     )
 );
 
-wire    [8:0]   op_result;
+wire    [ 8:0]  op_result;
+wire    [13:0]  full_result;
 
 jt12_op u_op(
     .rst            ( rst           ),
@@ -336,7 +337,8 @@ jt12_op u_op(
     .use_prev2      ( use_prev2     ),
     .use_prev1      ( use_prev1     ),
     .zero           ( zero          ),
-    .op_result      ( op_result     )
+    .op_result      ( op_result     ),
+    .full_result    ( full_result   )
 );
 
 wire signed [11:0] fm_snd_left, fm_snd_right;