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@jotego
jotego committed Nov 5, 2018
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4 changes: 4 additions & 0 deletions hdl/jt12_acc.v
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Expand Up @@ -24,6 +24,10 @@
Each channel can use the full range of the DAC as they do not
get summed in the real chip.
Operator data is summed up without adding extra bits. This is
the case of real YM3438, which was used on Megadrive 2 models.
*/


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154 changes: 77 additions & 77 deletions hdl/jt12_pg.v
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@@ -1,111 +1,111 @@
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2016
Based on information posted by Nemesis on:
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2016
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Based on jt51_phasegen.v, from JT51
*/
Based on jt51_phasegen.v, from JT51
*/

`timescale 1ns / 1ps

/*
tab size 4
tab size 4
*/

module jt12_pg(
input clk,
input clk_en,
input rst,
// Channel frequency
input [10:0] fnum_I,
input [ 2:0] block_I,
// Operator multiplying
input [ 3:0] mul_II,
// Operator detuning
input [ 2:0] dt1_I, // same as JT51's DT1
// phase modulation from LFO
input [ 6:0] lfo_mod,
input [ 2:0] pms_I,
// phase operation
input pg_rst_II,
input pg_stop, // not implemented
output reg [ 4:0] keycode_II,
output [ 9:0] phase_VIII
input clk,
input clk_en,
input rst,
// Channel frequency
input [10:0] fnum_I,
input [ 2:0] block_I,
// Operator multiplying
input [ 3:0] mul_II,
// Operator detuning
input [ 2:0] dt1_I, // same as JT51's DT1
// phase modulation from LFO
input [ 6:0] lfo_mod,
input [ 2:0] pms_I,
// phase operation
input pg_rst_II,
input pg_stop, // not implemented
output reg [ 4:0] keycode_II,
output [ 9:0] phase_VIII
);

wire [4:0] keycode_I;
wire signed [5:0] detune_mod_I;
reg signed [5:0] detune_mod_II;
wire [18:0] phinc_I;
reg [18:0] phinc_II;
wire [16:0] phinc_I;
reg [16:0] phinc_II;
wire [19:0] phase_drop, phase_in;
wire [ 9:0] phase_II;

always @(posedge clk) if(clk_en) begin
keycode_II <= keycode_I;
detune_mod_II <= detune_mod_I;
phinc_II <= phinc_I;
keycode_II <= keycode_I;
detune_mod_II <= detune_mod_I;
phinc_II <= phinc_I;
end

jt12_pg_comb u_comb(
.block ( block_I ),
.fnum ( fnum_I ),
// Phase Modulation
.lfo_mod ( lfo_mod[6:2] ),
.pms ( pms_I ),

// Detune
.detune ( dt1_I ),
.keycode ( keycode_I ),
.detune_out ( detune_mod_I ),
// Phase increment
.phinc_out ( phinc_I ),
// Phase add
.mul ( mul_II ),
.phase_in ( phase_drop ),
.pg_rst ( pg_rst_II ),
.detune_in ( detune_mod_II ),
.phinc_in ( phinc_II ),

.phase_out ( phase_in ),
.phase_op ( phase_II )
.block ( block_I ),
.fnum ( fnum_I ),
// Phase Modulation
.lfo_mod ( lfo_mod[6:2] ),
.pms ( pms_I ),

// Detune
.detune ( dt1_I ),
.keycode ( keycode_I ),
.detune_out ( detune_mod_I ),
// Phase increment
.phinc_out ( phinc_I ),
// Phase add
.mul ( mul_II ),
.phase_in ( phase_drop ),
.pg_rst ( pg_rst_II ),
.detune_in ( detune_mod_II ),
.phinc_in ( phinc_II ),

.phase_out ( phase_in ),
.phase_op ( phase_II )
);

jt12_sh_rst #( .width(20), .stages(24) ) u_phsh(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( phase_in ),
.drop ( phase_drop)
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( phase_in ),
.drop ( phase_drop)
);

jt12_sh_rst #( .width(10), .stages(6) ) u_pad(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( phase_II ),
.drop ( phase_VIII)
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( phase_II ),
.drop ( phase_VIII)
);

endmodule
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4 changes: 2 additions & 2 deletions hdl/jt12_pg_comb.v
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Expand Up @@ -37,14 +37,14 @@ module jt12_pg_comb(
output [ 4:0] keycode,
output signed [5:0] detune_out,
// Phase increment
output [18:0] phinc_out,
output [16:0] phinc_out,
// Phase add
input [ 3:0] mul,
input [19:0] phase_in,
input pg_rst,
// input signed [7:0] pm_in,
input signed [5:0] detune_in,
input [18:0] phinc_in,
input [16:0] phinc_in,

output [19:0] phase_out,
output [ 9:0] phase_op
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2 changes: 2 additions & 0 deletions hdl/jt12_pg_dt.v
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Expand Up @@ -20,6 +20,8 @@
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Note that detune produces an output even for fnum==0, is that correct?
Based on jt51_phasegen.v, from JT51
*/
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74 changes: 37 additions & 37 deletions hdl/jt12_pg_inc.v
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@@ -1,50 +1,50 @@
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 2-11-2018
Based on information posted by Nemesis on:
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 2-11-2018
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Based on jt51_phasegen.v, from JT51
*/
Based on jt51_phasegen.v, from JT51
*/

module jt12_pg_inc (
input [ 2:0] block,
input [10:0] fnum,
input signed [7:0] pm_offset,
output reg [18:0] phinc_pure
input [ 2:0] block,
input [10:0] fnum,
input signed [7:0] pm_offset,
output reg [16:0] phinc_pure
);

reg [12:0] fnum_mod;
reg [10:0] fnum_mod;

always @(*) begin
fnum_mod = { 1'b0, fnum, 1'b0 } + {{5{pm_offset[7]}},pm_offset};
case ( block )
3'd0: phinc_pure = { 8'd0, fnum_mod[12:2] };
3'd1: phinc_pure = { 7'd0, fnum_mod[12:1] };
3'd2: phinc_pure = { 6'd0, fnum_mod[12:0] };
3'd3: phinc_pure = { 5'd0, fnum_mod, 1'd0 };
3'd4: phinc_pure = { 4'd0, fnum_mod, 2'd0 };
3'd5: phinc_pure = { 3'd0, fnum_mod, 3'd0 };
3'd6: phinc_pure = { 2'd0, fnum_mod, 4'd0 };
3'd7: phinc_pure = { 1'd0, fnum_mod, 5'd0 };
endcase
fnum_mod = fnum + {{3{pm_offset[7]}},pm_offset};
case ( block )
3'd0: phinc_pure = { 7'd0, fnum_mod[10:1] };
3'd1: phinc_pure = { 6'd0, fnum_mod };
3'd2: phinc_pure = { 5'd0, fnum_mod, 1'd0 };
3'd3: phinc_pure = { 4'd0, fnum_mod, 2'd0 };
3'd4: phinc_pure = { 3'd0, fnum_mod, 3'd0 };
3'd5: phinc_pure = { 2'd0, fnum_mod, 4'd0 };
3'd6: phinc_pure = { 1'd0, fnum_mod, 5'd0 };
3'd7: phinc_pure = { fnum_mod, 6'd0 };
endcase
end

endmodule // jt12_pg_inc
9 changes: 5 additions & 4 deletions hdl/jt12_pg_sum.v
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Expand Up @@ -29,17 +29,18 @@ module jt12_pg_sum (
input [19:0] phase_in,
input pg_rst,
input signed [5:0] detune_signed,
input [18:0] phinc_pure,
input [16:0] phinc_pure,

output reg [19:0] phase_out,
output reg [ 9:0] phase_op
);

reg [19:0] phinc_premul, phinc_mul, ph_mod;
reg [16:0] phinc_premul;
reg [19:0] phinc_mul;

always @(*) begin
phinc_premul = {1'b0,phinc_pure} + {{14{detune_signed[5]}},detune_signed};
phinc_mul = ( mul==4'd0 ) ? (phinc_premul>>1) : (phinc_premul * mul);
phinc_premul = phinc_pure + {{11{detune_signed[5]}},detune_signed};
phinc_mul = ( mul==4'd0 ) ? {4'b0,phinc_premul[16:1]} : (phinc_premul * mul);

phase_out = pg_rst ? 20'd0 : (phase_in + phinc_mul);
phase_op = phase_out[19:10];
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7 changes: 6 additions & 1 deletion ver/verilator/jt12_test.cpp
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Expand Up @@ -186,6 +186,11 @@ int main(int argc, char** argv, char** env) {
cout << "All writes to MULT locked to 1\n";
writter.block( 0xF0, 0x30, [](int v){ return (v&0x70)|1;} );
continue;
}
if( string(argv[k])=="-nodt") {
cout << "All writes to DT locked to 1\n";
writter.block( 0xF0, 0x30, [](int v){ return (v&0x0F)|1;} );
continue;
}
if( string(argv[k])=="-nossg") {
cout << "All writes to SSG locked to 0\n";
Expand Down Expand Up @@ -240,7 +245,7 @@ int main(int argc, char** argv, char** env) {
top->addr = 0;
top->cs_n = 0;
top->wr_n = 1;
top->limiter_en=0;
top->limiter_en=1;
// cout << "Reset\n";
while( sim_time.get_time() < 256*PERIOD ) {
top->eval();
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