Skip to content

Merge version 1.2 of UART module to master. #2

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 8 commits into from
Dec 23, 2019
Merged

Merge version 1.2 of UART module to master. #2

merged 8 commits into from
Dec 23, 2019

Conversation

jakubcabal
Copy link
Owner

  • Added double FF for safe CDC.
  • Fixed fake received transaction after FPGA boot without reset.
  • Added more precisely clock dividers, dividing with rounding.
  • UART loopback example is for CYC1000 board now.

@jakubcabal jakubcabal changed the title Pull version 1.2 of UART module to master. Merge version 1.2 of UART module to master. Dec 23, 2019
@jakubcabal jakubcabal merged commit e556cb6 into master Dec 23, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
1 participant
@jakubcabal