Fix image references

tutorials/README.md

@@ -45,15 +45,15 @@ To maximally utilize the full power of the AI Engine, designers are encouraged t
 
 AI Engines are part of the larger Versal ACAP device and familiarity with other ACAP components such as the NoC, ARM processors, and custom PL components such as datamovers will help the designer integrate their AI Engine design into a larger ACAP system design.
 
-<p align="left"><img src="https://www.xilinx.com/content/xilinx/en/products/technology/ai-engine/_jcr_content/root/imageTabParsys/childParsys-overview/xilinxcolumns_copy_c_1601636194/childParsys-1/xilinximage.img.png/1622238572946.png" width="400"></p>
+<p align="left"><img src="images/intro1.png" width="400"></p>
 
 Within the AI Engine region of the device, there is an array of AI Engine tiles connected to one another through a number of communication structures (stream switches, local memories, and cascade streams). 
 
-<p align="left"><img src="https://docs.xilinx.com/api/khub/maps/scNYG4asFKV~nqnjEkGwmA/resources/4QKgSQwqrYtSReOmABmdBw/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=3.11.43" width="700"></p>
+<p align="left"><img src="images/intro3.png" width="700"></p>
 
 And within an AI Engine tile, we see an ISA-based VLIW Vector processor with its own program memory and register file, and its associated local data memory, which is shared with its immediate neighbors in a regular pattern (more on that later).
 
-<p align="left"><img src="https://docs.xilinx.com/api/khub/maps/q_Yc6QkQHbaC2~Qz9NTtmg/resources/g8M48UDPavKcSu6HWN65FQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=3.11.43" width="700"></p>
+<p align="left"><img src="images/intro2.png" width="700"></p>
 
 ## <ins>Communication</ins>
 Focusing back on communication, there are 3 primary ways AI Engines communicate with one another: 
@@ -68,13 +68,13 @@ For local memory, each AI Engine is able to access the local memory of its immed
 
 In the diagram below, we see data being communicated between AIE tiles through local memory in a pipelined or dataflow way.
 
-<p align="left"><img src="https://docs.xilinx.com/api/khub/maps/scNYG4asFKV~nqnjEkGwmA/resources/46TJtyJx_RF00BGX0ErAXA/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=3.11.43&filename=bzt1530655350975.image" width="600"></p>
+<p align="left"><img src="images/intro4.png" width="600"></p>
 
 ### <ins>Communication - Stream Switch</ins>
 
 The second way to communicate between AI Engines is through the stream switch which moves data up to 32-bits per cycle per stream. Here, data travels through stream switches throughout the AI Engine array from a source AIE tile to destination one. These stream paths can be circuit switched or packet switched and can be connected directly to stream ports at the AIE tile or read/written via DMAs. This is the second most common method of data communication and is the only method for moving data between non-adjacent tiles and into/out of the AI Engine array. The diagram below shows a streaming multicast example where streams are multicast from one AIE tile to 3 destinations.
 
-<p align="left"><img src="https://docs.xilinx.com/api/khub/maps/scNYG4asFKV~nqnjEkGwmA/resources/rJt9bOfzmlQdCPlCnG5_WQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=3.11.43&filename=ixc1530655536100.image" width="410"></p>
+<p align="left"><img src="images/intro5.png" width="410"></p>
 
 ### <ins>Communication - Cascade</ins>