DFCIR Specification

Dataflow Computer Intermediate Representation

Introduction

With the inception of heterogeneous computer systems (HCS) to address strict performance constraints by using application-specific hardware accelerators, in return this hardware becomes more complex to design. Streaming dataflow computers which focus on pipelined computations with cycle-by-cycle data reception and production require static scheduling of operations and further retiming. Dataflow Computer Intermediate Representation (DFCIR) leverages dataflow computer computation high-level specification, where each operation may or may not be specified with a pipeline depth and other timing characteristics.