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DFCxx -> SystemVerilog pipeline parametrization #24

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merged 1 commit into from
Jul 1, 2024
Merged

DFCxx -> SystemVerilog pipeline parametrization #24

merged 1 commit into from
Jul 1, 2024

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Muxianesty
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Mentioned in #23 .

DFCxx now supports different output paths for different artifacts.
Now an output path for SystemVerilog has to be set explicitly (option --out <PATH>)

@Muxianesty Muxianesty added the enhancement New feature or request label Jun 28, 2024
@Muxianesty Muxianesty requested a review from ssmolov June 28, 2024 21:23
@Muxianesty Muxianesty self-assigned this Jun 28, 2024
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ssmolov reviewed Jul 1, 2024
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When applying this PR, I receive a segmentation fault upon the following usage of the tool:

build/src/umain hls --config examples/polynomial2/polynomial2.json -l

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Muxianesty commented Jul 1, 2024 •
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When applying this PR, I receive a segmentation fault upon the following usage of the tool:

build/src/umain hls --config examples/polynomial2/polynomial2.json -l

I mentioned this in the PR's description: Now an output path for SystemVerilog has to be set explicitly (option --out <PATH>).
I didn't include this in README.md, because this PR is intermediate and README.md will change in another Pull Request with CLI being able to support different output formats.

@ssmolov ssmolov merged commit 43a210d into master Jul 1, 2024
@Muxianesty Muxianesty mentioned this pull request Jul 3, 2024
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@Muxianesty Muxianesty mentioned this pull request Jul 30, 2024
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@Muxianesty Muxianesty deleted the parametrize_pipeline branch August 15, 2024 14:15
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@ssmolov ssmolov ssmolov approved these changes

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@Muxianesty @ssmolov