refactor: add comments

iscas-tis · Dec 21, 2023 · 94a19a0 · 94a19a0
1 parent c6d1054
commit 94a19a0
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Showing 4 changed files with 38 additions and 31 deletions.
diff --git a/src/main/scala/rvspeccore/core/spec/instset/IBase.scala b/src/main/scala/rvspeccore/core/spec/instset/IBase.scala
@@ -16,7 +16,7 @@ import rvspeccore.core.spec.instset.csr._
   *     - Table 24.2: Instruction listing for RISC-V
   */
 trait IBaseInsts {
-  // RV32I Base Instruction Set
+  // - RV32I Base Instruction Set
   val LUI   = Inst("b????????????????????_?????_0110111")
   val AUIPC = Inst("b????????????????????_?????_0010111")
   val JAL   = Inst("b????????????????????_?????_1101111")
@@ -74,7 +74,7 @@ trait IBaseInsts {
   val ECALL  = Inst("b000000000000_00000_000_00000_1110011")
   val EBREAK = Inst("b000000000001_00000_000_00000_1110011")
 
-  // RV64I Base Instruction Set (in addition to RV32I)
+  // - RV64I Base Instruction Set (in addition to RV32I)
   val LWU = Inst("b???????_?????_?????_110_?????_0000011")
   val LD  = Inst("b???????_?????_?????_011_?????_0000011")
   val SD  = Inst("b???????_?????_?????_011_?????_0100011")
@@ -132,11 +132,6 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
     )
   }
 
-  /** RV32I Base Integer Instruction Set
-    *
-    *   - riscv-spec-20191213
-    *   - Chapter 2: RV32I Base Integer Instruction Set, Version 2.1
-    */
   def getfetchSize(): UInt = {
     MuxLookup(
       now.csr.misa(CSR.getMisaExtInt('C')),
@@ -147,6 +142,12 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
       )
     )
   }
+
+  /** RV32I Base Integer Instruction Set
+    *
+    *   - riscv-spec-20191213
+    *   - Chapter 2: RV32I Base Integer Instruction Set, Version 2.1
+    */
   def doRV32I: Unit = {
     // - 2.4 Integer Computational Instructions
     // - Integer Register-Immediate Instructions

diff --git a/src/main/scala/rvspeccore/core/spec/instset/MExtension.scala b/src/main/scala/rvspeccore/core/spec/instset/MExtension.scala
@@ -42,8 +42,8 @@ trait MExtensionInsts {
   */
 trait MExtension extends BaseCore with CommonDecode with MExtensionInsts {
   // - Table 7.1: Semantics for division by zero and division overflow.
-  // : L is the width of the operation in bits:
-  // : XLEN for DIV[U] and REM[U], or 32 for DIV[U]W and REM[U]W.
+  // : L is the width of the operation in bits: XLEN for DIV[U] and REM[U],
+  // : or 32 for DIV[U]W and REM[U]W.
   def opDIV(divisor: UInt, dividend: UInt, L: Int): UInt = {
     MuxCase(
       (divisor.asSInt / dividend.asSInt)(L - 1, 0).asUInt, // (L-1, 0) cut extra bit in double sign bit

diff --git a/src/main/scala/rvspeccore/core/spec/instset/Privileged.scala b/src/main/scala/rvspeccore/core/spec/instset/Privileged.scala
@@ -9,29 +9,38 @@ import rvspeccore.core.spec._
 import rvspeccore.core.tool.BitTool._
 import csr._
 
+/** Privileged Instructions
+  *
+  *   - riscv-privileged-20211203
+  *   - Chapter 9: RISC-V Privileged Instruction Set Listings
+  *     - Table 9.1: RISC-V Privileged Instructions
+  */
 trait PrivilegedInsts {
-  // - Privileged Insts Volume II
-  val SRET       = Inst("b000100000010_00000_000_00000_1110011")
-  val MRET       = Inst("b001100000010_00000_000_00000_1110011")
-  val WFI        = Inst("b0001000_00101_00000_000_00000_1110011")
-  val SFANCE_VMA = Inst("b0001001_?????_?????_000_00000_1110011")
+  // - Trap-Return Instructions
+  val SRET = Inst("b0001000_00010_00000_000_00000_1110011")
+  val MRET = Inst("b0011000_00010_00000_000_00000_1110011")
+  // - Interrupt-Management Instructions
+  val WFI = Inst("b0001000_00101_00000_000_00000_1110011")
+  // - Supervisor Memory-Management Instructions
+  val SFANCE_VMA      = Inst("b0001001_?????_?????_000_00000_1110011")
+  val SINVAL_VMA      = Inst("b0001011_?????_?????_000_00000_1110011") // not support yet
+  val SFANCE_W_INVAL  = Inst("b0001100_00000_00000_000_00000_1110011") // not support yet
+  val SFANCE_INVAL_IR = Inst("b0001100_00001_00000_000_00000_1110011") // not support yet
+  // - Hypervisor Memory-Management Instructions
+  val HFANCE_VVMA = Inst("b0010001_?????_?????_000_00000_1110011") // not support yet
+  val HFANCE_GVMA = Inst("b0110001_?????_?????_000_00000_1110011") // not support yet
+  val HINVAL_VVMA = Inst("b0010011_?????_?????_000_00000_1110011") // not support yet
+  val HINVAL_GVMA = Inst("b0110011_?????_?????_000_00000_1110011") // not support yet
+  // - Hypervisor Virtual-Machine Load and Store Instructions
+  // ...
+  // - Hypervisor Virtual-Machine Load and Store Instructions, RV64 only
+  // ...
+
   // FIXME: need to remove
   // val TEST_ILLEGAL=Inst("b0000000_00000_00000_000_00000_1111011")
   val TEST_TLBLW = Inst("b0000000_00000_00011_010_111010_000011")
-
-  // The above are instructions for Nutshell
-
-  val SINVAL_VMA      = Inst("b0001011_?????_?????_000_00000_1110011")
-  val SFANCE_W_INVAL  = Inst("b0001100_00000_00000_000_00000_1110011")
-  val SFANCE_INVAL_IR = Inst("b0001100_00001_00000_000_00000_1110011")
-
-  val HFANCE_VVMA = Inst("b0010001_?????_?????_000_00000_1110011")
-  val HFANCE_GVMA = Inst("b0110001_?????_?????_000_00000_1110011")
-  val HINVAL_VVMA = Inst("b0010011_?????_?????_000_00000_1110011")
-  val HINVAL_GVMA = Inst("b0110011_?????_?????_000_00000_1110011")
-  val NOP         = Inst("b0000000_00000_00000_000_00000_0000000")
-  // TODO: For more insts
-  // ......
+  // TODO: why has NOP?
+  val NOP = Inst("b0000000_00000_00000_000_00000_0000000")
 }
 
 /** “Privileged” Instruction-Fetch Fence Volume II Insts

diff --git a/src/main/scala/rvspeccore/core/spec/instset/csr/CSR.scala b/src/main/scala/rvspeccore/core/spec/instset/csr/CSR.scala
@@ -32,9 +32,6 @@ object CSRInfo {
   def apply(addrStr: String, width: Option[Int], rmask: UInt, wfn: UInt => UInt, wmask: UInt): CSRInfo = {
     new CSRInfo(addrStr.U(12.W), width, rmask, wfn, wmask)
   }
-  // def apply(addrStr: String, width: Option[Int], rmask: UInt, wmask: UInt): CSRInfo = {
-  //   new CSRInfo(addrStr.U(12.W), width, rmask, x=>x, wmask)
-  // }
 }
 
 /** All CSR informations