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Add aten::erfinv, aten::exp2, aten::expm1, aten::exponential_ #527

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merged 22 commits into from
Jul 20, 2024
Merged

Add aten::erfinv, aten::exp2, aten::expm1, aten::exponential_ #527

merged 22 commits into from
Jul 20, 2024

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hjhee
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@hjhee hjhee commented Jul 2, 2024

  • erfinv
  • erfinv_
  • erfinv.out
  • exp2
  • exp2_
  • exp2.out
  • expm1
  • expm1_
  • expm1.out
  • exponential_

@dvrogozh dvrogozh mentioned this pull request Jul 16, 2024
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@fengyuan14 fengyuan14 changed the title add aten::erfinv, aten::exp2, aten::expm1, aten::exponential_ Add aten::erfinv, aten::exp2, aten::expm1, aten::exponential_ Jul 17, 2024
@fengyuan14
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Please check the failure. Most likely we have different handle between GCC and SYCL compiler in std::exp2 for std::complex.
image

@hjhee
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hjhee commented Jul 18, 2024

Handling logic for CPU/XPU is not consistent for exp2:

cpu_results
tensor([nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj])
cuda_results
tensor([inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj,
        inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, 0.+0.j,
        0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j,
        0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj],
       device='xpu:0')
cpu_sample.input
tensor([inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf-infj, inf-infj, inf-infj, inf-infj, inf-infj,
        inf-infj, inf-infj, inf-infj, inf-infj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, -inf+infj,
        -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf-infj, -inf-infj, -inf-infj, -inf-infj, -inf-infj, -inf-infj,
        -inf-infj, -inf-infj, -inf-infj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, nan+infj, nan+infj,
        nan+infj, nan+infj, nan+infj, nan+infj, nan+infj, nan+infj, nan+infj, nan-infj, nan-infj, nan-infj, nan-infj, nan-infj, nan-infj, nan-infj,
        nan-infj, nan-infj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj])

@fengyuan14
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Handling logic for CPU/XPU is not consistent for exp2:

cpu_results
tensor([nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj])
cuda_results
tensor([inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj,
        inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, 0.+0.j,
        0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j,
        0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, 0.+0.j, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj,
        nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj],
       device='xpu:0')
cpu_sample.input
tensor([inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf+infj, inf-infj, inf-infj, inf-infj, inf-infj, inf-infj,
        inf-infj, inf-infj, inf-infj, inf-infj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, inf+nanj, -inf+infj,
        -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf+infj, -inf-infj, -inf-infj, -inf-infj, -inf-infj, -inf-infj, -inf-infj,
        -inf-infj, -inf-infj, -inf-infj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, -inf+nanj, nan+infj, nan+infj,
        nan+infj, nan+infj, nan+infj, nan+infj, nan+infj, nan+infj, nan+infj, nan-infj, nan-infj, nan-infj, nan-infj, nan-infj, nan-infj, nan-infj,
        nan-infj, nan-infj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj, nan+nanj])

We have met such kind of case in other std operators. We have different behavior for std::complex, which contains denormal value (nan or inf).

@fengyuan14
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When input is inf+infj, as the C++ standard, the output should be +-inf+nanj. XPU result should align with standard, but CPU result gets nan+nanj.
image

@fengyuan14 fengyuan14 added this pull request to the merge queue Jul 20, 2024
Merged via the queue into main with commit 2258cb4 Jul 20, 2024
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@fengyuan14 fengyuan14 deleted the hjhee/erfinv branch July 20, 2024 13:08
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