ROHD Blocking and Non-Blocking Assignment

[quekyj]

In the ROHD documentation, there is no mention of blocking and non-blocking assignments, as there is in System Verilog (https://nandland.com/blocking-vs-nonblocking-in-verilog/). The documentation only mentions the following:

To assign one signal to the value of another signal, use the <= operator. This is a hardware synthesizable assignment that connects two wires together.

Assignments within an _Always block should be executed conditionally, so use the < operator, which creates a ConditionalAssign object instead of <=.

In System Verilog's always block, you have the option to use <= or =. There is a difference between <= and < in the always block because it depends on your sensitivity list and the sequence of how you place the line. It affects the simulation result. Outside of the always block, there is only a single equal sign.

The question is, how does ROHD know when to use <= or < and how to use blocking and non-blocking assignment in ROHD?

[chykon]

The question is, how does ROHD know when to use <= or < and how to use blocking and non-blocking assignment in ROHD?

<= (assign in Verilog) is used outside of Combinational/Sequential blocks.

< (blocking/non-blocking assignment) is used inside Combinational/Sequential blocks.

For a blocking assignment use the Combinational block, for a non-blocking assignment use the Sequential block. ROHD does not allow mixing different assignment types in the same block.

More

ROHD has two logical assignment operators: <= and <.

<= (similar to assign from Verilog) cannot be used inside Combinational/Sequential procedural blocks. It should behave like Combinational with a single assignment (although there are still some problems with the equivalence of behavior (#286)), for example:

a0 <= b0;
d0 <= c0;

Combinational([
   a1 < b1
]);
Combinational([
   d1 < c1
]);

---

< is used for blocking or non-blocking assignment depending on the type of procedural block: Combinational (blocking), Sequential (non-blocking). Since ROHD clearly separates combinational (always_comb) and sequential (always_ff) logic, the user cannot mix different types of logic in the same procedural block (always) (see https://www.verilogpro.com/systemverilog-always_comb-always_ff/) .

[quekyj]

Wow, thanks for the explanation. The explanation is super clear. I wonder if we should add this into the documentation as well.