v0.3.0

[mkorbel1]

What's Changed

• Module hierarchy tracing fixes by @mkorbel1 in Module hierarchy tracing fixes #85
• Provide the ability to reserve instance names and provide + reserve definition names by @mkorbel1 in Provide the ability to reserve instance names and provide + reserve definition names #86
• Fix typo in README by @eric-norige in Fix typo in README #87
• Enhanced bin() to ignore '_'. Ticket - https://github.com/intel/rohd/… by @shubskmr in Enhanced bin() to ignore '_'. Ticket - https://github.com/intel/rohd/… #88
• Add explicit width to Const generated SystemVerilog by @mkorbel1 in Add explicit width to Const generated SystemVerilog #94
• Refactor to combine LogicValue and LogicValues into LogicValue, plus some related adjustments by @mkorbel1 in Refactor to combine LogicValue and LogicValues into LogicValue, plus some related adjustments #115
• Various features and testing for Logic and LogicValue by @mkorbel1 in Various features and testing for Logic and LogicValue #121

New Contributors

• @shubskmr made their first contribution in Enhanced bin() to ignore '_'. Ticket - https://github.com/intel/rohd/… #88

Full Changelog: v0.2.0...v0.3.0

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This discussion was created from the release v0.3.0.

[mkorbel1]

Version 0.3.0 of ROHD is now released officially at https://pub.dev/packages/rohd! This version brings a bunch of big quality of life improvements for working with ROHD.

The first thing you may notice is that LogicValues and LogicValue have been merged into one happy class called LogicValue. The LogicValues name has been deprecated, but most code should still work, just with deprecation warnings. This resolves an area of frequent confusion about what can be done with one bit versus one or more bits and swizzling between them.

There was previously a lot of inconsistency between the way LogicValue(s) worked compared to Logic, which was confusing when working with both to remember which functionality was available in which types. The API had treated LogicValues more like a List<LogicValue> rather than a "value" of a Logic signal. In v0.3.0, Logic and LogicValue now have a much more consistent API. For example both of them have a width instead of one having a length. As another example, both Logic and LogicValue have both getRange and slice, so that you can work with the one that makes the most sense for what you're working on.

A sometimes frustrating limitation in previous versions was that you couldn't do bitwise assignments to a Logic or LogicValues, which you could have done in SystemVerilog. To help here, v0.3.0 introduces the withSet function for both Logic and LogicValue. This function returns a copy with certain bits set to a new value, which adds a lot of convenience while still aligning with ROHD's approach to signal connectivity and value immutability. ROHD v0.3.0 also brings zeroExtend and signExtend to both Logic and LogicValue.

There are a variety of bug fixes and other more minor improvements as well. Check out the change log and API documentation for more details.

The changes in this release are mostly driven by user feedback, which is always extremely valuable. Hopefully these are welcome changes that make development using ROHD more pleasurable. Please continue to provide feedback, ask questions, file issues, and even contribute to the project!