Add Normal Mode Complete DDRT Training Status in Get/Set DDRT IO Init…

… Info Signed-off-by: MacKevin Fey <[email protected]>
intel · Jul 26, 2019 · 9c0fb49 · 9c0fb49
1 parent 2a3b4df
commit 9c0fb49
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Showing 4 changed files with 29 additions and 14 deletions.
diff --git a/DcpmPkg/common/NvmTypes.h b/DcpmPkg/common/NvmTypes.h
@@ -789,6 +789,7 @@ typedef struct _DEBUG_LOG_INFO {
 #define DDRT_TRAINING_COMPLETE      0x01
 #define DDRT_TRAINING_FAILURE       0x02
 #define DDRT_S3_COMPLETE            0x03
+#define NORMAL_MODE_COMPLETE        0x04
 #define DDRT_TRAINING_UNKNOWN       0xFF
 
 /** Dimm Boot Status Bitmask **/

diff --git a/DcpmPkg/driver/Core/Diagnostics/QuickDiagnostic.c b/DcpmPkg/driver/Core/Diagnostics/QuickDiagnostic.c
@@ -387,11 +387,12 @@ BootStatusDiagnosticsCheck(
   IN     CHAR16 *pDimmStr,
   IN OUT CHAR16 **ppResultStr,
   IN OUT UINT8 *pDiagState
-  )
+)
 {
   EFI_STATUS ReturnCode = EFI_SUCCESS;
   DIMM_BSR Bsr;
-  BOOLEAN FIS_1_14 = FALSE;
+  BOOLEAN FIS_GTE_1_14 = FALSE;
+  BOOLEAN FIS_GTE_2_01 = FALSE;
   UINT8 DdrtTrainingStatus = DDRT_TRAINING_UNKNOWN;
   EFI_DCPMM_CONFIG2_PROTOCOL *pNvmDimmConfigProtocol = NULL;
 
@@ -417,25 +418,33 @@ BootStatusDiagnosticsCheck(
   }
 
   /* Check to make sure the FW Version is bigger than 1.14*/
-  if (pDimm->FwVer.FwApiMajor == 1 && pDimm->FwVer.FwApiMinor >= 14) {
-    FIS_1_14 = TRUE;
+  if ((pDimm->FwVer.FwApiMajor == 1 && pDimm->FwVer.FwApiMinor >= 14) || pDimm->FwVer.FwApiMajor > 1) {
+    FIS_GTE_1_14 = TRUE;
+  }
+
+  /* Check to make sure the FW Version is bigger than 2.01*/
+  if ((pDimm->FwVer.FwApiMajor == 2 && pDimm->FwVer.FwApiMinor >= 1) || pDimm->FwVer.FwApiMajor > 2) {
+    FIS_GTE_2_01 = TRUE;
   }
 
-   ReturnCode = pNvmDimmConfigProtocol->GetBSRAndBootStatusBitMask(pNvmDimmConfigProtocol, pDimm->DimmID, &Bsr.AsUint64, NULL);
+  ReturnCode = pNvmDimmConfigProtocol->GetBSRAndBootStatusBitMask(pNvmDimmConfigProtocol, pDimm->DimmID, &Bsr.AsUint64, NULL);
 
   if (EFI_ERROR(ReturnCode)) {
     ReturnCode = EFI_DEVICE_ERROR;
     NVDIMM_WARN("Unable to get the DIMMs BSR.");
     APPEND_RESULT_TO_THE_LOG(pDimm, STRING_TOKEN(STR_QUICK_BSR_NOT_READABLE), EVENT_CODE_513, DIAG_STATE_MASK_FAILED, ppResultStr, pDiagState,
       pDimmStr);
-  } else {
+  }
+  else {
     if (Bsr.Separated_Current_FIS.Major == DIMM_BSR_MAJOR_NO_POST_CODE) {
       APPEND_RESULT_TO_THE_LOG(pDimm, STRING_TOKEN(STR_QUICK_BSR_BIOS_POST_TRAINING_FAILED), EVENT_CODE_519, DIAG_STATE_MASK_FAILED, ppResultStr, pDiagState,
         pDimmStr);
-    } else if (Bsr.Separated_Current_FIS.Major == DIMM_BSR_MAJOR_CHECKPOINT_INIT_FAILURE) {
+    }
+    else if (Bsr.Separated_Current_FIS.Major == DIMM_BSR_MAJOR_CHECKPOINT_INIT_FAILURE) {
       APPEND_RESULT_TO_THE_LOG(pDimm, STRING_TOKEN(STR_QUICK_BSR_FW_NOT_INITIALIZED), EVENT_CODE_520, DIAG_STATE_MASK_FAILED, ppResultStr, pDiagState,
         pDimmStr, Bsr.Separated_Current_FIS.Major, Bsr.Separated_Current_FIS.Minor);
-    } else if (Bsr.Separated_Current_FIS.Major == DIMM_BSR_MAJOR_CHECKPOINT_CPU_EXCEPTION) {
+    }
+    else if (Bsr.Separated_Current_FIS.Major == DIMM_BSR_MAJOR_CHECKPOINT_CPU_EXCEPTION) {
       APPEND_RESULT_TO_THE_LOG(pDimm, STRING_TOKEN(STR_QUICK_BSR_CPU_EXCEPTION), EVENT_CODE_537, DIAG_STATE_MASK_FAILED, ppResultStr, pDiagState,
         pDimmStr, Bsr.Separated_Current_FIS.Major, Bsr.Separated_Current_FIS.Minor);
     }
@@ -444,7 +453,8 @@ BootStatusDiagnosticsCheck(
     if (DdrtTrainingStatus == DDRT_TRAINING_UNKNOWN) {
       NVDIMM_DBG("Could not retrieve DDRT training status");
     }
-    if (DdrtTrainingStatus != DDRT_TRAINING_COMPLETE && DdrtTrainingStatus != DDRT_S3_COMPLETE) {
+    if ((!FIS_GTE_2_01 && DdrtTrainingStatus != DDRT_TRAINING_COMPLETE && DdrtTrainingStatus != DDRT_S3_COMPLETE)
+      || (FIS_GTE_2_01 && DdrtTrainingStatus != DDRT_TRAINING_COMPLETE && DdrtTrainingStatus != DDRT_S3_COMPLETE && DdrtTrainingStatus != NORMAL_MODE_COMPLETE)) {
       APPEND_RESULT_TO_THE_LOG(pDimm, STRING_TOKEN(STR_QUICK_BSR_DDRT_IO_NOT_COMPLETE), EVENT_CODE_538, DIAG_STATE_MASK_FAILED, ppResultStr, pDiagState,
         pDimmStr);
     }
@@ -456,7 +466,7 @@ BootStatusDiagnosticsCheck(
       APPEND_RESULT_TO_THE_LOG(pDimm, STRING_TOKEN(STR_QUICK_AIT_DRAM_NOT_READY), EVENT_CODE_533, DIAG_STATE_MASK_FAILED, ppResultStr, pDiagState,
         pDimmStr);
     }
-    if (FIS_1_14) {
+    if (FIS_GTE_1_14) {
       if ((Bsr.Separated_Current_FIS.DTS == DDRT_TRAINING_NOT_COMPLETE) ||
         (Bsr.Separated_Current_FIS.DTS == DDRT_TRAINING_FAILURE)) {
         APPEND_RESULT_TO_THE_LOG(pDimm, STRING_TOKEN(STR_QUICK_DDRT_TRAINING_NOT_COMPLETE_FAILED), EVENT_CODE_543, DIAG_STATE_MASK_FAILED, ppResultStr, pDiagState,

diff --git a/DcpmPkg/driver/Core/NvmDimmPassThru.h b/DcpmPkg/driver/Core/NvmDimmPassThru.h
@@ -1326,6 +1326,7 @@ typedef struct {
     0x01 - Training Complete
     0x02 - Training Failure
     0x03 - S3 Complete
+    0x04 - Normal Mode Complete
   **/
   UINT8 DdrtTrainingStatus; //!<Designates training has been completed by BIOS.
   UINT8 Reserved[126];

diff --git a/DcpmPkg/driver/Protocol/Driver/NvmDimmConfig.c b/DcpmPkg/driver/Protocol/Driver/NvmDimmConfig.c
@@ -432,13 +432,14 @@ EFI_STATUS
 PopulateDimmBootStatusBitmask(
   IN     DIMM_BSR *pBsr,
   IN     DIMM *pDimm,
-     OUT UINT16 *pBootStatusBitmask
-  )
+  OUT UINT16 *pBootStatusBitmask
+)
 {
   EFI_STATUS ReturnCode = EFI_SUCCESS;
 
   UINT16 BootStatusBitmask = 0;
   UINT8 DdrtTrainingStatus = DDRT_TRAINING_UNKNOWN;
+  BOOLEAN FIS_GTE_2_01 = FALSE;
 
   NVDIMM_ENTRY();
 
@@ -449,7 +450,8 @@ PopulateDimmBootStatusBitmask(
 
   if ((pBsr->AsUint64 == MAX_UINT64_VALUE) || (pBsr->AsUint64 == 0)) {
     BootStatusBitmask = DIMM_BOOT_STATUS_UNKNOWN;
-  } else {
+  }
+  else {
     if (pBsr->Separated_Current_FIS.MR == DIMM_BSR_MEDIA_NOT_TRAINED) {
       BootStatusBitmask |= DIMM_BOOT_STATUS_MEDIA_NOT_READY;
     }
@@ -463,7 +465,8 @@ PopulateDimmBootStatusBitmask(
     if (DdrtTrainingStatus == DDRT_TRAINING_UNKNOWN) {
       NVDIMM_DBG("Could not retrieve DDRT training status");
     }
-    if (DdrtTrainingStatus != DDRT_TRAINING_COMPLETE && DdrtTrainingStatus != DDRT_S3_COMPLETE) {
+    if ((!FIS_GTE_2_01 && DdrtTrainingStatus != DDRT_TRAINING_COMPLETE && DdrtTrainingStatus != DDRT_S3_COMPLETE)
+      || (FIS_GTE_2_01 && DdrtTrainingStatus != DDRT_TRAINING_COMPLETE && DdrtTrainingStatus != DDRT_S3_COMPLETE && DdrtTrainingStatus != NORMAL_MODE_COMPLETE)) {
       BootStatusBitmask |= DIMM_BOOT_STATUS_DDRT_NOT_READY;
     }
     if (pBsr->Separated_Current_FIS.MBR == DIMM_BSR_MAILBOX_NOT_READY) {