Intel® FPGA Partial Reconfiguration Design Flow
Release Notes Version v18.0.0_1
This release has been verified using Intel Quartus® Prime Pro Edition Software Version 18.0.0 Build 219
Related Links:
- Main project page : https://01.org/fpga-partial-reconfig
- Github repository : https://github.com/01org/fpga-partial-reconfig
- Intel FPGA website: http://www.altera.com
Key Features of Partial Reconfiguration in Quartus Prime Pro Edition v18.0.0
The Intel FPGA Partial Reconfiguration Design Flow release version v18.0.0_1 is a simplified Partial Reconfiguration flow comparing to the v17.1.0_1 version: it does not use synthesis revisions anymore; all the steps can be done through the GUI as well as the command line; we do not need to generate any flow scripts to compile the implementation revisions. The Intel FPGA Partial Reconfiguration Design Flow release version v18.0.0_1 includes the following new features and enhancements:
- Tutorials
- Intel Stratix 10
- Intel Stratix 10 Traditional PR
- Updated version of the Stratix 10 PR tutorial for the Stratix 10 GX Development kit
- Includes all sources files and application note
- Intel Stratix 10 Hierarchical PR
- Updated version of the Stratix 10 HPR tutorial for the Stratix 10 GX Development kit
- Includes all sources files and application note
- Intel Stratix 10 Static Update PR
- Updated version of the Stratix 10 SUPR tutorial for the Stratix 10 GX Development kit
- Includes all sources files and application note
- Intel Stratix 10 PR + Signa l Tap
- New Signal Tap tutorial for Intel Stratix 10 PR design
- Includes all sources files and application note
- Intel Stratix 10 Traditional PR
- Intel Arria 10
- Intel Arria 10 Traditional PR
- Updated version of the Arria 10 PR tutorial for the Arria 10 GX Development kit
- Includes all sources files and application note
- Intel Arria 10 Hierarchical PR
- Updated version of the Arria 10 HPR tutorial for the Arria 10 GX Development kit
- Includes all sources files and application note
- Intel Arria 10 Static Update PR
- Updated version of the Arria 10 SUPR tutorial for the Arria 10 GX Development kit
- Includes all sources files and application note
- Intel Arria 10 PR + Signa l Tap
- New Signal Tap tutorial for Intel Arria 10 PR design
- Includes all sources files and application note
- Intel Arria 10 Traditional PR
- Intel Stratix 10
- Reference designs
- Intel Stratix 10
- Intel Stratix 10 Traditional PR reference design
- Updated version of the Stratix 10 PR over PCIe reference design for the Stratix 10 GX Development kit
- Includes all sources files and application note
- Includes PCIe Linux driver with upstreamed components and example host utility
- Intel Stratix 10 Hierarchical PR reference design
- Updated version of the Stratix 10 HPR over PCIe reference design for the Stratix 10 GX Development kit
- Includes all sources files and application note
- Includes PCIe Linux driver with upstreamed components and example host utility
- Intel Stratix 10 Traditional PR reference design
- Intel Arria 10
- Intel Arria 10 Traditional PR reference design
- Updated version of the Arria 10 PR over PCIe reference design for the Arria 10 GX Development kit
- Includes all sources files and application note
- Includes PCIe Linux driver with upstreamed components and example host utility
- Arria 10 Hierarchical PR reference design
- Updated version of the Arria 10 HPR over PCIe reference design for the Arria 10 GX Development kit
- Includes all sources files and application note
- Includes PCIe Linux driver with upstreamed components and example host utility
- Intel Arria 10 Traditional PR reference design
- Linux Driver
- Updated FPGA-PCIe driver for PCIe attached FPGAs. The provided example host program demonstrates how easy it is to access the FPGA region's address space from user-level program.
- Intel Stratix 10
Linux driver files are licensed under GPL2. Unless otherwise stated, all files are licensed under the terms of the MIT Open Source license. See the file named LICENSE in the root of the release for complete details.