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Merge pull request #68 from intel/prep140
changes for version 1.4.0
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1.3.11 | ||
1.4.0 |
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########################################################################################################### | ||
# Copyright (C) 2021-2023 Intel Corporation | ||
# SPDX-License-Identifier: BSD-3-Clause | ||
########################################################################################################### | ||
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# Icelake event list for platforms that don't have support for the fixed counter TMA events, e.g., some AWS | ||
# VMs. | ||
# Note that there are no more than 10 events per group. On these same platforms, the cpu-cycles fixed | ||
# counter is not supported so a general purpose counter will be used. | ||
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cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, | ||
cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, | ||
cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, | ||
cpu/event=0xc3,umask=0x01,cmask=0x01,edge=0x01,period=100003,name='MACHINE_CLEARS.COUNT'/, | ||
cpu/event=0xc5,umask=0x00,period=50021,name='BR_MISP_RETIRED.ALL_BRANCHES'/, | ||
cpu/event=0xf1,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, | ||
cpu/event=0x79,umask=0x08,cmask=0x00,period=2000003,name='IDQ.DSB_UOPS'/, | ||
cpu/event=0xa8,umask=0x01,cmask=0x00,period=2000003,name='LSD.UOPS'/, | ||
cpu/event=0x48,umask=0x02,period=1000003,name='L1D_PEND_MISS.FB_FULL_PERIODS'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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# events for TMA metrics without fixed counter support (group 1) | ||
cpu/event=0x9c,umask=0x01,name='IDQ_UOPS_NOT_DELIVERED.CORE'/, | ||
cpu/event=0xa4,umask=0x01,name='TOPDOWN.SLOTS_P'/, | ||
cpu/event=0x80,umask=0x04,name='ICACHE_DATA.STALLS'/, | ||
cpu/event=0x83,umask=0x04,name='ICACHE_TAG.STALLS'/, | ||
cpu/event=0x79,umask=0x30,name='IDQ.MS_SWITCHES'/, | ||
cpu/event=0x87,umask=0x01,name='DECODE.LCP'/, | ||
cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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# events for TMA metrics without fixed counter support (group 2) | ||
cpu/event=0xab,umask=0x02,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, | ||
cpu/event=0xa4,umask=0x02,name='TOPDOWN.BACKEND_BOUND_SLOTS'/, | ||
cpu/event=0x0D,umask=0x01,name='INT_MISC.CLEARS_COUNT'/, | ||
cpu/event=0xc2,umask=0x02,name='UOPS_RETIRED.SLOTS'/, | ||
cpu/event=0xd0,umask=0x83,name='MEM_INST_RETIRED.ANY'/, | ||
cpu/event=0xc4,umask=0x00,name='BR_INST_RETIRED.ALL_BRANCHES'/, | ||
cpu/event=0x9c,umask=0x01,cmask=0x05,period=1000003,name='IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, | ||
cpu/event=0xa3,umask=0x0C,cmask=0x0C,period=1000003,name='CYCLE_ACTIVITY.STALLS_L1D_MISS'/, | ||
cpu/event=0xa3,umask=0x14,cmask=0x14,period=2000003,name='CYCLE_ACTIVITY.STALLS_MEM_ANY'/, | ||
cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, | ||
cpu/event=0xa3,umask=0x04,cmask=0x04,period=1000003,name='CYCLE_ACTIVITY.STALLS_TOTAL'/, | ||
cpu/event=0xa6,umask=0x02,period=2000003,name='EXE_ACTIVITY.1_PORTS_UTIL'/, | ||
cpu/event=0xa6,umask=0x04,period=2000003,name='EXE_ACTIVITY.2_PORTS_UTIL'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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cpu/event=0xd0,umask=0x21,cmask=0x00,period=100007,name='MEM_INST_RETIRED.LOCK_LOADS'/, | ||
cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, | ||
cpu/event=0xd1,umask=0x40,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, | ||
cpu/event=0xd1,umask=0x08,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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cpu/event=0xa3,umask=0x05,cmask=0x05,period=1000003,name='CYCLE_ACTIVITY.STALLS_L2_MISS'/, | ||
cpu/event=0xa3,umask=0x06,cmask=0x06,period=1000003,name='CYCLE_ACTIVITY.STALLS_L3_MISS'/, | ||
cpu/event=0xa3,umask=0x0c,cmask=0x0c,period=1000003,name='CYCLE_ACTIVITY.STALLS_L1D_MISS'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, | ||
cpu/event=0x79,umask=0x04,cmask=0x05,period=2000003,name='IDQ.MITE_CYCLES_OK'/, | ||
cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, | ||
cpu/event=0x79,umask=0x08,cmask=0x05,period=2000003,name='IDQ.DSB_CYCLES_OK'/, | ||
cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, | ||
cpu/event=0x14,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIVIDER_ACTIVE'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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cpu/event=0x79,umask=0x04,period=100003,name='IDQ.MITE_UOPS'/, | ||
cpu/event=0x79,umask=0x30,period=100003,name='IDQ.MS_UOPS'/, | ||
cpu/event=0x56,umask=0x01,period=100003,name='UOPS_DECODED.DEC0'/, | ||
cpu/event=0x56,umask=0x01,cmask=0x01,period=100003,name='UOPS_DECODED.DEC0:c1'/, | ||
cpu/event=0x0e,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/, | ||
cpu-cycles:k, | ||
ref-cycles:k, | ||
instructions:k; | ||
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# OCR | ||
cpu/event=0xb7,umask=0x01,offcore_rsp=0x104000477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/, | ||
cpu/event=0xb7,umask=0x01,offcore_rsp=0x84002380,name='OCR.HWPF_L3.L3_MISS_LOCAL'/, | ||
cpu/event=0x85,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, | ||
cpu/event=0x08,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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cpu/event=0xb7,umask=0x01,offcore_rsp=0x1030000477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, | ||
cpu/event=0xb7,umask=0x01,offcore_rsp=0x830000477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, | ||
cpu/event=0xb7,umask=0x01,offcore_rsp=0x730000477,name='OCR.READS_TO_CORE.REMOTE_DRAM'/, | ||
cpu/event=0xb7,umask=0x01,offcore_rsp=0x90002380,name='OCR.HWPF_L3.REMOTE'/, | ||
cpu/event=0x08,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, | ||
cpu/event=0x49,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, | ||
cpu-cycles, | ||
ref-cycles, | ||
instructions; | ||
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# C6 | ||
cstate_core/c6-residency/; | ||
cstate_pkg/c6-residency/; | ||
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# UPI | ||
upi/event=0x2,umask=0xf,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; | ||
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# CHA | ||
cha/event=0x00,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; | ||
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cha/event=0x35,umask=0xC8177E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, | ||
cha/event=0x35,umask=0xC816FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, | ||
cha/event=0x35,umask=0xC896FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, | ||
cha/event=0x35,umask=0xC8977E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; | ||
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cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; | ||
cha/event=0x35,umask=0xc88ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF'/, | ||
cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, | ||
cha/event=0x36,umask=0xC816FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/; | ||
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cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD'/, | ||
cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, | ||
cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, | ||
cha/event=0x36,umask=0xC817FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; | ||
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# memory read/writes | ||
imc/event=0x04,umask=0x0f,name='UNC_M_CAS_COUNT.RD'/, | ||
imc/event=0x04,umask=0x30,name='UNC_M_CAS_COUNT.WR'/; | ||
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# power | ||
power/energy-pkg/, | ||
power/energy-ram/; |
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