Remove LPSPI chip select type state, and other refactors #180
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mciantyre
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We're testing unsafe code in the HAL. Make sure miri is happy with that unsafe code. We build with minimal optimizations by default, no matter the target. Turn those off during the miri invocation.
When we support the embedded-hal 1.0 traits, we should distinguish between the bus -- having the data and clock pins -- and the device(s), which have the chip select. Removing the chip select type state is the first step in supporting this interface. Temporarily enable PCS0 in the board setup routines. This keeps the examples working as expected.
We'll need something like this when we implement SPI devices.
This'll make it easier to associate bus state with each transaction.
Default behavior is unchanged, in that the mode is still set by the user's `Lpspi::set_mode` value. But now users could define it as part of a one-off transaction.
On the RT1180, these two fields are WO/RAZ. Since we can't trust the hardware to retrieve these values for us, we cache them in memory. Writes will behave as before. The driver ensures that all accesses on CCR pass through the cache.
This specific configuration isn't different on the 1180. However, the LPI2C and LPUART FIFOs are 2x and 4x larger, respectively, on the 1180. I was afraid that I was using constants in the LPI2C and LPUART drivers, like I was here. But those two drivers look OK; it was just LPSPI that's assuming a FIFO size.
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Most of these commits support a larger change that implements embedded-hal
SpiBusandSpiDevice(#181). They also anticipate support for the 1180. See commit messages for details.Although some of these may be backwards compatible, I'm not immediately back-porting them onto v0.5. Let me know if something seems useful.
Closes #131, since it provides a way to select and change the LPSPI hardware chip select. Also closes #149; this PR has a similar breaking change.