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This adds support for setting source clock and dividers for FlexIO clock roots in accordance with the RMs
This is WIP because I haven't gotten around to testing the current version on actual hardware yet, but I'd like feedback on the general approach.
The issue here is that FLEXIO1_CLK_ROOT on 1010/1020 is FLEXIO2_CLK_ROOT on 106x, so there is some magic involved in getting the module names and doc comments right. Due to this it might also make sense to move this into a separate module and re-export it.