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fix: use "VREF" as the vref node instead of searching for it.
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harshkhandeparkar committed Sep 7, 2023
1 parent ac74588 commit 98fa8d5
Showing 1 changed file with 3 additions and 293 deletions.
296 changes: 3 additions & 293 deletions openfasoc/generators/ldo-gen/tools/simulations.py
Original file line number Diff line number Diff line change
@@ -1,16 +1,7 @@
import math
import numpy as np
import os
import re
import shutil
import sys
import subprocess as sp
import matplotlib.pyplot as plt
from cairosvg import svg2png
from PIL import Image
from scipy.interpolate import make_interp_spline
import ltspice
import pandas as pd

# ------------------------------------------------------------------------------
# Create Sim Directories
Expand Down Expand Up @@ -115,7 +106,8 @@ def process_PEX_netlist(rawExtractedNetlistPath, simtool, designName):
"""Prepare PEX netlist for simulations. Return string containing the netlist."""
with open(rawExtractedNetlistPath, "r") as spice_in:
netlist = spice_in.read()
vref_node_to = re.findall(r"\bcapacitor_test_nf_\S*", netlist)[0]

vref_node_to = "VREF"
head = re.search(r"\.subckt " + designName + r" .*\n(\+.*\n)*", netlist, re.I)[0]
newhead = " ".join(head.split(" ") + ["\n+ " + vref_node_to + "\n"])
netlist = netlist.replace(head, newhead)
Expand All @@ -139,7 +131,7 @@ def process_PEX_netlist(rawExtractedNetlistPath, simtool, designName):
netlist = netlist.replace("$", ";")
return [
netlist,
newhead.replace(vref_node_to, "VREF")
newhead
.replace(designName, "", 1)
.replace(".subckt", "", 1)
.replace("r_VREG", "VREG", 1),
Expand All @@ -155,288 +147,6 @@ def process_PEX_netlist(rawExtractedNetlistPath, simtool, designName):
+ std_pt_in_cnt[4] std_pt_in_cnt[5] std_pt_in_cnt[6] std_pt_in_cnt[7] std_pt_in_cnt[8]
+ trim1 trim10 trim2 trim3 trim4 trim5 trim6 trim7 trim8 trim9 VDD VSS VREF VREG"""


def ngspice_prepare_scripts(
head,
cap_list,
templateScriptDir,
sim_dir,
user_specs,
arrSize,
pdk_path,
freq_list,
model_corner,
pex,
):
"""Specializes ngspice simulations and returns (string) bash to run all sims."""
designName = user_specs["designName"]
vref = user_specs["vin"]
max_load = user_specs["imax"]
model_file = pdk_path + "/libs.tech/ngspice/sky130.lib.spice"
with open(templateScriptDir + "ldo_tran_ngspice.sp", "r") as sim_spice:
sim_template = sim_spice.read()
sim_template = sim_template.replace("@model_file", model_file)
sim_template = sim_template.replace("@model_corner", model_corner)
sim_template = sim_template.replace("@design_nickname", designName)
sim_template = sim_template.replace("@VALUE_REF_VOLTAGE", str(vref))
sim_template = sim_template.replace("@Res_Value", str(1.2 * vref / max_load))
if pex:
sim_template = sim_template.replace("@proper_pin_ordering", head)
else:
sim_template = sim_template.replace(
"@proper_pin_ordering", prePEX_SPICE_HEADER_GLOBAL_V
)
# create list of scripts to run (wheretocopy, filename, stringdata, ngspicecommand)
scripts_to_run = list()
for freq in freq_list:
sim_script = sim_template
sim_script = sim_script.replace("@clk_period", str(1 / freq))
sim_script = sim_script.replace("@duty_cycle", str(0.5 / freq))
sim_time = 1.2 * arrSize / freq
sim_script = sim_script.replace("@sim_time", str(sim_time))
sim_script = sim_script.replace("@sim_step", str(sim_time / 2000))
if freq == 100000:
freq_name = "0.1MHz"
elif freq == 1000000:
freq_name = "1.0MHz"
else:
freq_name = "10.0MHz"
load = max_load * 1000
for cap in cap_list:
sim_script_f = sim_script.replace("@Cap_Value", str(cap))
output_raw = (
str(load) + "mA_" + freq_name + "_" + str(cap) + "_cap_output.raw"
)
sim_script_f = sim_script_f.replace("@output_raw", str(output_raw))
sim_name = (
"ldo_tran_" + str(load) + "mA_" + freq_name + "_" + str(cap) + ".sp"
)
scripts_to_run.append(
tuple(
(
sim_dir,
sim_name,
sim_script_f,
"ngspice -b -o "
"ldo_" + freq_name + "_" + str(cap) + "_out.txt -i " + sim_name,
)
)
)
# add power array script to the list
with open(templateScriptDir + "/pwrarr_sweep_ngspice.sp", "r") as sim_spice:
pwr_sim_template = sim_spice.read()
pwr_sim_template = pwr_sim_template.replace("@model_corner", model_corner)
pwr_sim_template = pwr_sim_template.replace("@VALUE_REF_VOLTAGE", str(vref))
pwr_sim_template = pwr_sim_template.replace("@model_file", model_file)
scripts_to_run.append(
tuple(
(
sim_dir,
"pwrarr.sp",
pwr_sim_template,
"ngspice -b -o pwrout.txt -i pwrarr.sp",
)
)
)
# add load chnage script to list
with open(templateScriptDir + "/ldo_load_change_ngspice.sp", "r") as sim_spice:
load_sim_template = sim_spice.read()
load_sim_template = load_sim_template.replace("@model_corner", model_corner)
load_sim_template = load_sim_template.replace("@VALUE_REF_VOLTAGE", str(vref))
load_sim_template = load_sim_template.replace("@model_file", model_file)
load_sim_template = load_sim_template.replace(
"@Res_Value", str(1.2 * vref / max_load)
)
sim_time = 1.2 * arrSize / 1000000
load_sim_template = load_sim_template.replace("@sim_time", str(sim_time))
load_sim_template = load_sim_template.replace("@sim_step", str(sim_time / 2000))
output_raw = str(load) + "mA_output_load_change.raw"
load_sim_template = load_sim_template.replace("@output_raw", str(output_raw))
sim_name = "ldo_load_change.sp"
if pex:
load_sim_template = load_sim_template.replace("@proper_pin_ordering", head)
else:
load_sim_template = load_sim_template.replace(
"@proper_pin_ordering", prePEX_SPICE_HEADER_GLOBAL_V
)
scripts_to_run.append(
tuple(
(
sim_dir,
sim_name,
load_sim_template,
"ngspice -b -o ldo_load_change.txt -i " + sim_name,
)
)
)
# write scripts to their respective locations and create sim_list for simulations
raw_data = []
sim_list = []
for script in scripts_to_run:
with open(script[0] + "/" + script[1], "w") as scriptfile:
scriptfile.write(script[2])
shutil.copy2(
os.path.abspath(templateScriptDir) + "/.spiceinit",
os.path.abspath(script[0]),
)
sim_list.append(script[3])
for freq in freq_list:
if freq == 100000:
freq_name = "0.1MHz"
elif freq == 1000000:
freq_name = "1.0MHz"
else:
freq_name = "10.0MHz"
for cap in cap_list:
raw_data.append(
str(load) + "mA_" + freq_name + "_" + str(cap) + "_cap_output.raw"
)
return [sim_list, raw_data]


def xyce_prepare_scripts(
head,
cap_list,
templateScriptDir,
sim_dir,
user_specs,
arrSize,
pdk_path,
freq_list,
model_corner,
pex,
):
"""Specializes xyce simulations and returns (string) bash to run all sims."""
designName = user_specs["designName"]
vref = user_specs["vin"]
max_load = user_specs["imax"]
model_file = pdk_path + "/libs.tech/ngspice/sky130.lib.spice"
with open(templateScriptDir + "ldo_tran_xyce.sp", "r") as sim_spice:
sim_template = sim_spice.read()
sim_template = sim_template.replace("@model_file", model_file)
sim_template = sim_template.replace("@model_corner", model_corner)
sim_template = sim_template.replace("@design_nickname", designName)
sim_template = sim_template.replace("@VALUE_REF_VOLTAGE", str(vref))
sim_template = sim_template.replace("@Res_Value", str(1.2 * vref / max_load))
if pex:
sim_template = sim_template.replace("@proper_pin_ordering", head)
else:
sim_template = sim_template.replace(
"@proper_pin_ordering", prePEX_SPICE_HEADER_GLOBAL_V
)
# create list of scripts to run (wheretocopy, filename, stringdata, ngspicecommand)
scripts_to_run = list()
for freq in freq_list:
sim_script = sim_template
sim_script = sim_script.replace("@clk_period", str(1 / freq))
sim_script = sim_script.replace("@duty_cycle", str(0.5 / freq))
sim_time = 1.2 * arrSize / freq
sim_script = sim_script.replace("@sim_time", str(sim_time))
sim_script = sim_script.replace("@sim_step", str(sim_time / 2000))
if freq == 100000:
freq_name = "0.1MHz"
elif freq == 1000000:
freq_name = "1.0MHz"
else:
freq_name = "10.0MHz"
load = max_load * 1000
for cap in cap_list:
sim_script_f = sim_script.replace("@Cap_Value", str(cap))
output_raw = (
str(load) + "mA_" + freq_name + "_" + str(cap) + "_cap_output.raw"
)
sim_script_f = sim_script_f.replace("@output_raw", str(output_raw))
sim_name = (
"ldo_tran_" + str(load) + "mA_" + freq_name + "_" + str(cap) + ".sp"
)
scripts_to_run.append(
tuple(
(
sim_dir,
sim_name,
sim_script_f,
"Xyce -o "
"ldo_"
+ freq_name
+ "_"
+ str(cap)
+ "_out.log -hspice-ext all "
+ sim_name,
)
)
)
# add power array script to the list
with open(templateScriptDir + "/pwrarr_sweep_xyce.sp", "r") as sim_spice:
pwr_sim_template = sim_spice.read()
pwr_sim_template = pwr_sim_template.replace("@model_corner", model_corner)
pwr_sim_template = pwr_sim_template.replace("@VALUE_REF_VOLTAGE", str(vref))
pwr_sim_template = pwr_sim_template.replace("@model_file", model_file)
scripts_to_run.append(
tuple(
(
sim_dir,
"pwrarr.sp",
pwr_sim_template,
"Xyce -o pwrout.log -hspice-ext all pwrarr.sp",
)
)
)
# add load chnage script to list
with open(templateScriptDir + "/ldo_load_change_xyce.sp", "r") as sim_spice:
load_sim_template = sim_spice.read()
load_sim_template = load_sim_template.replace("@model_corner", model_corner)
load_sim_template = load_sim_template.replace("@VALUE_REF_VOLTAGE", str(vref))
load_sim_template = load_sim_template.replace("@model_file", model_file)
load_sim_template = load_sim_template.replace(
"@Res_Value", str(1.2 * vref / max_load)
)
sim_time = 1.2 * arrSize / 1000000
load_sim_template = load_sim_template.replace("@sim_time", str(sim_time))
load_sim_template = load_sim_template.replace("@sim_step", str(sim_time / 2000))
output_raw = str(load) + "mA_output_load_change.raw"
load_sim_template = load_sim_template.replace("@output_raw", str(output_raw))
sim_name = "ldo_load_change.sp"
if pex:
load_sim_template = load_sim_template.replace("@proper_pin_ordering", head)
else:
load_sim_template = load_sim_template.replace(
"@proper_pin_ordering", prePEX_SPICE_HEADER_GLOBAL_V
)
scripts_to_run.append(
tuple(
(
sim_dir,
sim_name,
load_sim_template,
"Xyce -o ldo_load_change.log -hspice-ext all " + sim_name,
)
)
)
# write scripts to their respective locations and prepare sim list for simulations
raw_data = []
sim_list = []
for script in scripts_to_run:
with open(script[0] + "/" + script[1], "w") as scriptfile:
scriptfile.write(script[2])
shutil.copy2(
os.path.abspath(templateScriptDir) + "/.spiceinit",
os.path.abspath(script[0]),
)
sim_list.append(script[3])
for freq in freq_list:
if freq == 100000:
freq_name = "0.1MHz"
elif freq == 1000000:
freq_name = "1.0MHz"
else:
freq_name = "10.0MHz"
for cap in cap_list:
raw_data.append(
str(load) + "mA_" + freq_name + "_" + str(cap) + "_cap_output.raw"
)
return [sim_list, raw_data]


# ------------------------------------------------------------------------------
# max current binary search (deprecated, instead use dc linear sweep)
# ------------------------------------------------------------------------------
Expand Down

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