Architecture Version I, Release v1.0
It has passed almost all inspections, and the architecture works well.
Implemented Instruction Set
- RV32I: full
- RV32C: full
- RV32M: partially, exclude MULH, MULHSU, MULHU, DIVU, REMU.
- RV32A: not supported
- RV32F: not supported
- RV32D: not supported, but the register is ready.
- RV32Zicsr: not supported
Features
- Implemented RV32IC
- Real-Time Dis-Assembler is ready. (integrated into the decoder)
- Easy debugging interface, via DBG material.
- Configuration API is ready (unstable), via CFG material.
- Direct memory access interface using FILT and RAM, serialization, and deserialization are possible.
- Supports up to a maximum operating frequency of 2.04 kHz (60 FPS)
- Unaligned(or misaligned) memory is accessible in 2-byte increments.
Next Update
For the time being, only bug fixes will be made.