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Update RGB CPLD to V94, Improved calibration, switchable timing sets, Apple IIGS, Apple Lisa support #229

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merged 79 commits into from
Aug 8, 2021
Merged

Update RGB CPLD to V94, Improved calibration, switchable timing sets, Apple IIGS, Apple Lisa support #229

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35588fb
Fix CGA artifact quality and optimise CPU usage
IanSB May 30, 2021
7468549
Add sampling phase in degrees. Also make Apple II default for YUV CPLD
IanSB Jun 8, 2021
25bbc35
Add apple IIGS line length compensation and change FBsize values for …
IanSB Jun 12, 2021
c4c9906
Update profiles
IanSB Jun 15, 2021
ad2fa8a
Generalise mode7 second timing set to support alternate sets with oth…
IanSB Jun 15, 2021
77d1449
Fix issues with auto ntsc artifact detection with Tandy CoCo
IanSB Jun 15, 2021
cf72a9e
Update Amiga CPLD files
IanSB Jun 15, 2021
7c1c8a2
Rearrange bit flags and add single button timing set switch
IanSB Jun 16, 2021
e4e9be3
Reduce display time for timing set switch
IanSB Jun 17, 2021
23213da
Update Apple IIGS profiles
IanSB Jun 18, 2021
0c0638b
Fix issue with saving sampling phase >7 on 6847 profiles
IanSB Jun 18, 2021
7df4063
Update firmware folder
IanSB Jun 28, 2021
e7cb1d0
Update profiles
IanSB Jun 28, 2021
ce79681
Update profiles
IanSB Jun 30, 2021
000b7ea
Update profiles
IanSB Jun 30, 2021
ba5261d
Add Apple IIGS auto switching support and fix some artifact switching…
IanSB Jun 30, 2021
b723527
Update RGB CPLD to V93 with Apple IIGS autoswitch detection
IanSB Jun 30, 2021
2e2e973
Update 6847 palette generation
IanSB Jul 3, 2021
bef3a3d
Update profiles
IanSB Jul 3, 2021
1365951
Change SW3 to adjust NTSC phase quadrant in artifact mode
IanSB Jul 3, 2021
f9b683c
Update profiles
IanSB Jul 4, 2021
17c8edb
Add FFOSD on/off menu option (previously always on)
IanSB Jul 4, 2021
68b142b
Update profiles
IanSB Jul 5, 2021
45b3048
Update firmware folder
IanSB Jul 5, 2021
5db02a1
Add support for CPLD v94 with 9 bpp + blank and 1bpp on vsync and syn…
IanSB Jul 5, 2021
064c4e1
Further support for 1bpp vsync and auto config sample phasing
IanSB Jul 5, 2021
33f7c77
Update profiles
IanSB Jul 5, 2021
59615b7
Ignore flashing cursors when auto calibrating
IanSB Jul 6, 2021
2a01b1a
Optimise line capture loop and fix edge bug in NTSC artifact mode
IanSB Jul 6, 2021
390ef45
Improve sync loss handling
IanSB Jul 6, 2021
1ccc33b
Fix equivalence calculation
IanSB Jul 6, 2021
ca740f2
Fix some bugs with CPLD driver
IanSB Jul 8, 2021
ebfb972
Update firmware folder
IanSB Jul 8, 2021
20001b6
Update profiles
IanSB Jul 8, 2021
511a020
Fix more bugs with RGB CPLD driver
IanSB Jul 8, 2021
df4d6db
Move force erase CPLD code earlier before code that might lockup with…
IanSB Jul 9, 2021
bda121a
Fix 6847 artifact detection
IanSB Jul 12, 2021
3f652e3
Improve cache preload by doing it in situ in the main loop
IanSB Jul 12, 2021
98509ee
Improve logging message
IanSB Jul 12, 2021
6e57a35
NTSC artifact fix defs
IanSB Jul 12, 2021
a53e177
Update profiles
IanSB Jul 12, 2021
8dd2664
Improve CPLD erase feature
IanSB Jul 14, 2021
a43c44b
Add hsync edge delay for Apple Lisa
IanSB Jul 14, 2021
bcf7533
Update firmware folder
IanSB Jul 14, 2021
c186db2
Update profiles
IanSB Jul 14, 2021
44c621d
Update profiles
IanSB Jul 14, 2021
a406be9
Update profiles
IanSB Jul 14, 2021
2ea5e73
Use dummy screen for cache preload
IanSB Jul 15, 2021
0d2550e
Ignore cyan on first couple of pixels in coco artifact mode
IanSB Jul 15, 2021
93c95e8
Update led status when no video connected
IanSB Jul 16, 2021
65313c3
Update palettes for 6847
IanSB Jul 16, 2021
20c0614
Update profiles including missing EGA 40 column profile
IanSB Jul 17, 2021
b853df1
Improve 90/270 degree sample phase selection
IanSB Jul 18, 2021
525ea31
Fix black character colour on some 6847 palettes
IanSB Jul 18, 2021
c911dd0
Update profiles
IanSB Jul 23, 2021
e2fda6a
Fix sync detection PLL recalibration
IanSB Jul 23, 2021
a81ad5c
Update 6847 palette
IanSB Jul 24, 2021
e855b0b
Update profiles
IanSB Jul 24, 2021
e9f71b4
Update profiles
IanSB Jul 24, 2021
0606a8a
update profiles
IanSB Jul 24, 2021
86ce2e1
fix led flicker rate
IanSB Jul 24, 2021
529b09d
Update profiles
IanSB Jul 28, 2021
6f934ae
Add save config option to auto calibration
IanSB Jul 28, 2021
5af4af9
Update profiles
IanSB Jul 28, 2021
220506d
Add calibration reminder
IanSB Jul 28, 2021
424e42f
Add support for custom resolutions with custom refresh rates
IanSB Jul 29, 2021
79809bc
Increase timeout after calibration
IanSB Jul 30, 2021
7ac529c
Update sampling phase message
IanSB Jul 30, 2021
2dd1f56
Fix timing and detection issues with Apple IIGS
IanSB Aug 2, 2021
80fbabd
Update profiles
IanSB Aug 2, 2021
a453737
Update profiles
IanSB Aug 2, 2021
13c4fd8
Update profiles
IanSB Aug 2, 2021
f3f5b11
Update profiles
IanSB Aug 2, 2021
3960732
Update profiles
IanSB Aug 2, 2021
c3b3078
Add Apple IIGS autoswitch option without manual override
IanSB Aug 4, 2021
0eed880
Update RGB CPLD to v9.4
IanSB Aug 4, 2021
a66d14d
Update profiles
IanSB Aug 4, 2021
39f3bf3
Improve aspect ratio of screencaps when using interpolated scaling
IanSB Aug 7, 2021
4fddc30
Fix issue with divider changing during auto calibrate in mode 7
IanSB Aug 7, 2021
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36 changes: 34 additions & 2 deletions src/capture_line_default_twelvebits_8bpp_16bpp.S
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Original file line number Diff line number Diff line change
Expand Up @@ -94,8 +94,8 @@ preload_capture_line_default_eightbits_8bpp:
capture_line_default_twelvebits_16bpp:
push {lr}
SETUP_VSYNC_DEBUG_16BPP_R11
tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
bne OSD_capture_line_default_twelvebits_16bpp
tst r3, #BITDUP_ENABLE_FFOSD | BITDUP_ENABLE_GREY_DETECT
bne TEST_capture_line_default_twelvebits_16bpp

SKIP_PSYNC_NO_OLD_CPLD
SETUP_TWELVE_BITS_MASK_R14
Expand Down Expand Up @@ -125,6 +125,38 @@ loop_16bpp:

pop {r0, pc}

TEST_capture_line_default_twelvebits_16bpp:
tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
bne OSD_capture_line_default_twelvebits_16bpp

SKIP_PSYNC_NO_OLD_CPLD
SETUP_TWELVE_BITS_MASK_R14
TEST_loop_16bpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_HI r5 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_HI r6 // input in r8

WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_HI r7 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_HI r10 // input in r8

WRITE_R5_R6_R7_R10_16BPP

subs r1, r1, #1
bne TEST_loop_16bpp

pop {r0, pc}

OSD_capture_line_default_twelvebits_16bpp:
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
Expand Down
10 changes: 2 additions & 8 deletions src/capture_line_fast_simple_16bpp.S
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Original file line number Diff line number Diff line change
Expand Up @@ -23,9 +23,6 @@
// Pixel in GPIO 13.. 2 -> 15.. 0
and r9, r8, r14
eor r10, \reg, r9, lsr #(PIXEL_BASE)
eor r9, r9, #(GREY_PIXELS & 0x0ff) << PIXEL_BASE
eors r9, r9, #(GREY_PIXELS & 0xf00) << PIXEL_BASE
bicne r3, #BITDUP_LINE_CONDITION_DETECTED
tst r8, #MUX_MASK
orrne r3, #BITDUP_FFOSD_DETECTED
.endm
Expand All @@ -34,9 +31,6 @@
// Pixel in GPIO 13.. 2 -> 31.. 16
and r9, r8, r14
eor \reg, r10, r9, lsl #(16 - PIXEL_BASE)
eor r9, r9, #(GREY_PIXELS & 0x0ff) << PIXEL_BASE
eors r9, r9, #(GREY_PIXELS & 0xf00) << PIXEL_BASE
bicne r3, #BITDUP_LINE_CONDITION_DETECTED
.endm

.macro OSD_SIMPLE_CAPTURE_TWELVE_BITS_16BPP_LO reg
Expand Down Expand Up @@ -206,7 +200,7 @@ capture_line_fast_simple_trailing_pos_16bpp:
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
bic r3, r3, #PSYNC_MASK // only +ve edge (inverted later)
tst r3, #BIT_OSD
tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
bne OSD_capture_line_fast_simple_trailing_pos_16bpp
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
COMMON_SIMPLE
Expand All @@ -230,7 +224,7 @@ capture_line_fast_simple_leading_pos_16bpp:
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
bic r3, r3, #PSYNC_MASK // only +ve edge (inverted later)
tst r3, #BIT_OSD
tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
bne OSD_capture_line_fast_simple_leading_pos_16bpp
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
COMMON_SIMPLE
Expand Down
40 changes: 36 additions & 4 deletions src/capture_line_fast_twelvebits_8bpp_16bpp.S
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -94,12 +94,44 @@ preload_capture_line_fast_eightbits_8bpp:
capture_line_fast_twelvebits_16bpp:
push {lr}
SETUP_VSYNC_DEBUG_16BPP_R11
tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
bne OSD_capture_line_fast_twelvebits_16bpp
tst r3, #BITDUP_ENABLE_FFOSD | BITDUP_ENABLE_GREY_DETECT
bne TEST_capture_line_fast_twelvebits_16bpp

SKIP_PSYNC_NO_OLD_CPLD_FAST
SETUP_TWELVE_BITS_MASK_R14
loop_16bpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_TWELVE_BITS_16BPP_HI r5 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_TWELVE_BITS_16BPP_HI r6 // input in r8

WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_TWELVE_BITS_16BPP_HI r7 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_TWELVE_BITS_16BPP_HI r10 // input in r8
stmia r0!, {r5, r6, r7, r10}

subs r1, r1, #1
bne loop_16bpp

mov r0, r2
pop {pc}

TEST_capture_line_fast_twelvebits_16bpp:
tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
bne OSD_capture_line_fast_twelvebits_16bpp

SKIP_PSYNC_NO_OLD_CPLD_FAST
SETUP_TWELVE_BITS_MASK_R14
TEST_loop_16bpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
Expand All @@ -120,14 +152,14 @@ loop_16bpp:
stmia r0!, {r5, r6, r7, r10}

subs r1, r1, #1
bne loop_16bpp
bne TEST_loop_16bpp

mov r0, r2
pop {pc}

OSD_capture_line_fast_twelvebits_16bpp:
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
SKIP_PSYNC_NO_OLD_CPLD_FAST
SETUP_TWELVE_BITS_MASK_R14
OSD_loop_16bpp:
Expand Down
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