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USB2 INNO PHY 驱动修改 #9

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USB2 INNO PHY 驱动修改 #9

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9f6ef85
phy: hisi-inno-phy: add support for hi3798mv200-usb2-phy
185264646 Feb 16, 2024
c6d4888
phy: hisilicon: hisi-inno-phy: enable clocks for every ports
185264646 Feb 16, 2024
3a3e904
dt-bindings: phy: hisi-inno-usb2: convert to YAML
185264646 Feb 16, 2024
2ad41ab
dt-bindings: phy: hisilicon,inno-usb2-phy: add support for Hi3798MV10…
185264646 Mar 3, 2024
3ef3290
dt-bindings: phy: hisi-inno-usb2: add compatible of hisilicon,hi3798m…
185264646 Mar 3, 2024
6260c8e
phy: hisilicon: hisi-inno-phy: add support for Hi3798MV200 INNO PHY
185264646 Feb 16, 2024
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phy: hisilicon: hisi-inno-phy: enable clocks for every ports 
This is needed for port1 to work.

Fixes: ba8b0ee ("phy: add inno-usb2-phy driver for hi3798cv200 SoC")
Signed-off-by: Yang Xiwen <[email protected]>
@185264646
185264646 committed Mar 3, 2024
commit c6d48881286326c9297ef0e306b8ef8a6f4e2e97
4 changes: 3 additions & 1 deletion drivers/phy/hisilicon/phy-hisi-inno-usb2.c
View file
Original file line number Diff line number Diff line change
@@ -86,8 +86,10 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,

static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
{
int i;
/* The phy clk is controlled by the port0 register 0x06. */
hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE);
for (i = 0; i < INNO_PHY_PORT_NUM; i++)
hisi_inno_phy_write_reg(priv, i, 0x06, PHY_CLK_ENABLE);
msleep(PHY_CLK_STABLE_TIME);
}