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mv200的时钟驱动 #15

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Hi3559 clock drivers implemented their own PLL driver. Unfortunately
our generic PLL driver will use a same name. So add a prefix "_" to
avoid that.

Signed-off-by: Yang Xiwen <[email protected]>
Add support for PLL used by various HiSilicon SoCs

Signed-off-by: Yang Xiwen <[email protected]>
This SoC is similar to Hi3798CV200 with a few more clocks in CRG module.

Note this driver is still ongoing, many clocks are not registered in the
driver now. Feedback is welcomed, especially from HiSilicon people.
# Describe the purpose of this series. The information you put here
# will be used by the project maintainer to make a decision whether
# your patches should be reviewed, and in what priority order. Please be
# very detailed and link to any relevant discussions or sites that the
# maintainer can review to better understand your proposed changes. If you
# only have a single patch in your series, the contents of the cover
# letter will be appended to the "under-the-cut" portion of the patch.

# Lines starting with # will be removed from the cover letter. You can
# use them to add notes or reminders to yourself. If you want to use
# markdown headers in your cover letter, start the line with ">#".

# You can add trailers to the cover letter. Any email addresses found in
# these trailers will be added to the addresses specified/generated
# during the b4 send stage. You can also run "b4 prep --auto-to-cc" to
# auto-populate the To: and Cc: trailers based on the code being
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To: Michael Turquette <[email protected]>
To: Stephen Boyd <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Conor Dooley <[email protected]>
Cc: David Yang <[email protected]>
Cc:  <[email protected]>
Cc:  <[email protected]>
Cc:  <[email protected]>
Signed-off-by: Yang Xiwen <[email protected]>

---
Changes in v6:
- add support for PLLs
- Link to v5: https://lore.kernel.org/r/[email protected]

Changes in v5:
- sort compatibles alphabetically (Rob Herring)
- squash patch 5&6 (Rob Herring)
- Link to v4: https://lore.kernel.org/r/[email protected]

Changes in v4:
- dt-bindings: hisi-crg: add reg and #reset-cells to required, add reset-controller to required for cv200
- dt-bindings: hisi-crg: do not add "simple-mfd" and "syscon" for hi3519 (Krzysztof Kozlowski)
- dt-bindings: hi3798mv200: replace spaces with tabs (Krzysztof Kozlowski)
- dt-bindings: s/DTS/DT_BINDINGS_CLOCK (Krzysztof Kozlowski)
- Link to v3: https://lore.kernel.org/r/[email protected]

Changes in v3:
- remove RFC (Krzysztof Kozlowski)
- rearrange patches so dt-binding comes before drivers (Krzysztof Kozlowski)
- dt-bindings: Remove lots of properties
- dt-bindings: stop merging all hisi-clock bindings, only convert hisi-crg.txt for now.
- dt-bindings: remove hisilicon,hisi-sdmmc-dll subnode (Rob Herring, Krzysztof Kozlowski)
- split histb-clock.h into two files, deprecate this header file
- fix all users (hi3798cv200.dtsi and hi3798cv200 CRG driver)
- hi3798mv200-crg: add a few missing clocks
- Link to v2: https://lore.kernel.org/r/[email protected]

Changes in v2:
- s/dt-binding/dt-bindings in commit logs: (Krzysztof Kozlowski)
- fix bot error by adding "hisilicon,hisi-sdmmc-dll" to syscon.yaml (Rob Herring)
- hi3798mv200-crg: assign fixed rate parents to some gates
- hi3798mv200-crg: s/ETH/FEMAC, add GMAC ctrl clock
- Link to v1: https://lore.kernel.org/r/[email protected]

--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
  "series": {
    "revision": 6,
    "change-id": "20240216-clk-mv200-cc8cae396ee0",
    "prefixes": [],
    "history": {
      "v1": [
        "[email protected]"
      ],
      "v2": [
        "[email protected]"
      ],
      "v3": [
        "[email protected]"
      ],
      "v4": [
        "[email protected]"
      ],
      "v5": [
        "[email protected]"
      ]
    }
  }
}
Also rename to hisilicon,hisi-crg.yaml. While at it, add "syscon" and
"simple-mfd" compatibles to match the existing hi3798cv200.dtsi.

Add reset-controller subnode for hisilicon,hi3798cv200-crg to match the
existing hi3798cv200.dtsi.

Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Yang Xiwen <[email protected]>
The CRG driver between different SoCs provides different clocks and
resets. We should not provide a generic header file across all HiSTB
SoCs, instead each CRG driver should provide its own.

Split histb-clock.h into two files: hisilicon,hi3798cv200-crg.h and
hisilicon,hi3798cv200-sysctrl.h. This header file is for Hi3798CV200
only actually. For other HiSTB SoCs, some clock definitions are missing.

Create a new histb-clock.h to include these two files for backward
compatibility only. Deprecate this file as well.

Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Yang Xiwen <[email protected]>
The generic histb-clock.h header is now deprecated. Fix it by including
individual binding header files directly instead.

Signed-off-by: Yang Xiwen <[email protected]>
histb-clock.h is now deprecated. Include hisilicon,hi3798cv200-crg.h and
hisilicon-sysctrl.h directly instead.

Signed-off-by: Yang Xiwen <[email protected]>
This SoC is similar to Hi3798CV200.  A few clock number definitions
are also added.

Acked-by: Rob Herring <[email protected]>
Signed-off-by: Yang Xiwen <[email protected]>
Add CRG driver for Hi3798MV200 SoC. CRG(Clock and Reset Generator) module
generates clock and reset signals used by other module blocks on SoC.

Only currently used clocks are added. Clocks without mainline user are omitted.

Notably PLLs are missing due to the lack of PLL driver.

Signed-off-by: Yang Xiwen <[email protected]>
@185264646 185264646 requested a review from yangfl February 25, 2024 13:59
@yangfl yangfl deleted the branch histb-mainline:histb March 3, 2024 11:21
@yangfl yangfl closed this Mar 3, 2024
@yangfl yangfl reopened this Mar 3, 2024
yangfl pushed a commit that referenced this pull request Sep 17, 2024
A sysfs reader can race with a device reset or removal, attempting to
read device state when the device is not actually present. eg:

     [exception RIP: qed_get_current_link+17]
  #8 [ffffb9e4f2907c48] qede_get_link_ksettings at ffffffffc07a994a [qede]
  #9 [ffffb9e4f2907cd8] __rh_call_get_link_ksettings at ffffffff992b01a3
 #10 [ffffb9e4f2907d38] __ethtool_get_link_ksettings at ffffffff992b04e4
 #11 [ffffb9e4f2907d90] duplex_show at ffffffff99260300
 #12 [ffffb9e4f2907e38] dev_attr_show at ffffffff9905a01c
 #13 [ffffb9e4f2907e50] sysfs_kf_seq_show at ffffffff98e0145b
 #14 [ffffb9e4f2907e68] seq_read at ffffffff98d902e3
 #15 [ffffb9e4f2907ec8] vfs_read at ffffffff98d657d1
 torvalds#16 [ffffb9e4f2907f00] ksys_read at ffffffff98d65c3f
 torvalds#17 [ffffb9e4f2907f38] do_syscall_64 at ffffffff98a052fb

 crash> struct net_device.state ffff9a9d21336000
    state = 5,

state 5 is __LINK_STATE_START (0b1) and __LINK_STATE_NOCARRIER (0b100).
The device is not present, note lack of __LINK_STATE_PRESENT (0b10).

This is the same sort of panic as observed in commit 4224cfd
("net-sysfs: add check for netdevice being present to speed_show").

There are many other callers of __ethtool_get_link_ksettings() which
don't have a device presence check.

Move this check into ethtool to protect all callers.

Fixes: d519e17 ("net: export device speed and duplex via sysfs")
Fixes: 4224cfd ("net-sysfs: add check for netdevice being present to speed_show")
Signed-off-by: Jamie Bainbridge <[email protected]>
Link: https://patch.msgid.link/8bae218864beaa44ed01628140475b9bf641c5b0.1724393671.git.jamie.bainbridge@gmail.com
Signed-off-by: Jakub Kicinski <[email protected]>
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