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PLL #11

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PLL #11

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207b104
clk: hisilicon: add support for PLL
185264646 Feb 24, 2024
4ff16b0
clk: hisilicon: rename hi3519 PLL registration function
185264646 Feb 24, 2024
1806d28
clk: hisilicon: add support for PLL
185264646 Feb 24, 2024
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clk: hisilicon: rename hi3519 PLL registration function 
Hi3559 clock drivers implemented their own PLL driver. Unfortunately
our generic PLL driver will use a same name. So add a prefix "_" to
avoid that.

Signed-off-by: Yang Xiwen <[email protected]>
@185264646
185264646 committed Feb 24, 2024
commit 4ff16b0551b7775f55ed2b8406ac17aca1e2891e
4 changes: 2 additions & 2 deletions drivers/clk/hisilicon/clk-hi3559a.c
View file
Original file line number Diff line number Diff line change
@@ -452,7 +452,7 @@ static const struct clk_ops hisi_clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
};

static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
static void _hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
int nums, struct hisi_clock_data *data, struct device *dev)
{
void __iomem *base = data->base;
@@ -517,7 +517,7 @@ static struct hisi_clock_data *hi3559av100_clk_register(
if (ret)
return ERR_PTR(ret);

hisi_clk_register_pll(hi3559av100_pll_clks,
_hisi_clk_register_pll(hi3559av100_pll_clks,
ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev);

ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg,