VideoCore IV 3d Graphics Pipeline
(Note: whether this should be named VideoCore graphics pipeline isn't obvious, but for the sake of simplicity we use this name).
This page contains some initial understanding of the RaspberryPi's 2835 graphics pipeline.
- Basic graphics understanding (pixels, colours, rasterisation/rendering).
- Understanding of PowerVR's Tile Based Deferred Rendering ( TBDR ), Intel's Zone Rendering ( ZBR ) US6762765, Gigapixel's work.
- Familiarity with OpenGL ES 2.x Pixel and Vertex shaders.
- Fabien Giesen's A trip through the Graphics Pipeline 2011.
Functional blocks/stages of the Shader processor are:
- CP - Control Processor.
- VCM - Vertex Cache Manager.
- VCD - Vertex Cache DMA.
- PTB - Primitive Tile Binner.
- PSE - Primitive Setup Engine.
- FEP - Front-End Pipe.
- CAP - Coverage Accumulate Pipe.
- TLB - Tile Buffer.
- QVI - Interpolator.
- QUC - Uniforms Cache.
- QIC - Instruction Cache.
- TL2 - Texture Unit L2 Cache.
- TMU - Texture and Memory Lookup Unit (with small L1 cache).
- QSH - QPU Scheduler.
- VPM - Vertex and Primitive Memory.
- QPU - Quad Processor Unit (floating point shader processors).
Possible Configuration for 24 gigaflops:
- 32x32 pixel tiles.
- 3 slices of:
- QVI, Coeffs Memory, QUC, QIC, TMU
- 4x QPU
- Fed by a shared common pipeline of CP, VCM, VCD, PTB, FEP, CAP, TLB, QSH and VPM.
Overview:
US20110148901: [0037] In operation, the mobile multimedia processor 102 may be adapted to perform tile mode rendering in two separate phases. A first phase may comprise a binning process or operation and a second phase may comprise a rendering process or operation. During the first or binning phase, it may be determined which pixel tiles in a screen plane are covered or overlapped by each graphic primitive associated with a video frame, for example. During this phase, an ordered list of primitives and/or state-change data for each tile may be built. A coordinate shader may be utilized to perform at least some of the operations associated with the binning phase. The list or lists generated during the binning phase may comprise indices (e.g., vertex indices) that make reference to a table that comprises attributes of the vertices of the primitives. In some embodiments of the invention, the indices in the list or lists may be compressed. During the second or rendering phase, the contents associated with each pixel tile may be drawn or rendered. The rendering phase may utilize the list or lists generated during the binning phase that provide a reference to the vertex attributes of the primitives located within the tile. The vertex attributes may be brought into local memory on a tile-by-tile basis, for example. A vertex shader may be utilized to perform at least some of the operations of the rendering phase. Once a pixel tile is rendered, the rendered pixels may be pushed to main memory, for example, and a similar approach may be followed with other pixel tiles.
First Phase
[0050] The 3D pipeline 218 may comprise a tile mode architecture in which a rendering operation may be separated into a first phase and a second phase. During the first phase, the 3D pipeline 218 may utilize a coordinate shader to perform a binning operation.
Second Phase
[0051] During the second phase, the 3D pipeline 218 may utilize a vertex shader to render images such as those in frames in a video sequence, for example. A vertex shader may be typically utilized to transform a 3D position of a vertex from a graphics primitive such as triangles or polygons, for example, in a virtual space to a corresponding two-dimensional (2D) coordinate at on a screen plane. A vertex shader may also be utilized to obtain a depth value for a Z-buffer for a vertex. A vertex shader may process various vertex properties such as color, position, and/or texture coordinates. The output of a vertex shader may be utilized by a geometry shader and/or a rasterizer, for example. Because the coordinate shader utilized in the first phase need not generate a complete set of vertex properties that can be produced by a typical full vertex shader, those values need not be stored for later use, which may result in reduced memory and/or bandwidth requirements.
A Coordinate Shader is a shader derived automatically from a Vertex Shader. The coordinate shader generates sufficient information to perform the binning operation, without wasting computational effort of applying the full vertex shader in the instance the primitive is eliminated. For example, a coordinate shader avoids applying lighting and texturing calculations.
US20110148901: The coordinate shader may be obtained from a vertex shader at compile time, for example. In one embodiment of the invention, the coordinate shader may be obtained automatically during vertex shader compilation. The coordinate shader may comprise those portions of the vertex shader that relate to the processing of the coordinates of the vertices. Such coordinates may be utilized to, for example, control the binning operation and need not be stored for subsequent use such as during the second phase, for example.
- Fixed length instruction word of 64 bits.
- Instructions contain multiple issue slots.
- There is a slot for the Add vector ALU and Multiply vector ALU.
- Registers written in one cycle, should not be read back for 1 instruction cycle.
- Branch instructions have 3 delay slots.
- Thread switching is handled by (cooperative) thread switch instructions.
- Program may be terminated by instruction with program end signal, two delay slots will be executed before the unit becomes idle.