revive cache replacement policy

def/memory.param.def

@@ -191,6 +191,34 @@ param<SHARED_MEM_CYCLES, shared_mem_cycles, uns8, 4>
 param<SHARED_MEM_PORTS, shared_mem_ports, uns, 2>
 
 
+/* Cache Replacement Policy */ 
+param<RRIP_CACHE_NUM_BIT, rrip_cache_num_bit, int, 3>
+param<RRIP_CACHE_INSERT_AT, rrip_cache_insert_at, int, 6>
+param<RRIP_CACHE_NUM_COUNTER_BIT, rrip_cache_num_counter_bit, int, 10>
+param<RRIP_CACHE_DYNAMIC_ON, rrip_cache_dynamic_on, bool, false>
+param<RRIP_CACHE_BIP_EPSILON, rrip_cache_bip_epsilon, int, 5>
+param<RRIP_CACHE_FOR_GPU, rrip_cache_for_gpu, bool, false> 
+param<RRIP_CACHE_FOR_MULTI_GPU, rrip_cache_for_multi_gpu, bool, false> 
+param<RRIP_CACHE_PROBABILITY, rrip_cache_probability, int, 20>
+param<RRIP_BIP_ALWAYS, rrip_bip_always, bool, false>
+param<CACHE_FOR_STREAM_CPU, cache_for_stream_cpu, bool, false>
+
+param<TADIP_CACHE_NUM_COUNTER_BIT, tadip_cache_num_counter_bit, int, 10>
+param<TADIP_CACHE_BIP_EPSILON, tadip_cache_bip_epsilon, int, 5>
+
+param<UCP_CACHE_NUM_APPLICATION, ucp_cache_num_application, int, 2>
+param<UCP_CACHE_PARTITION_PERIOD, ucp_cache_partition_period, int, 5000000>
+param<UCP_CACHE_FOR_GPU, ucp_cache_for_gpu, bool, false>
+param<UCP_CACHE_FOR_MULTI_GPU, ucp_cache_for_multi_gpu, bool, false>
+param<UCP_CACHE_CPU_INTERFERENCE, ucp_cache_cpu_interference, int, 50>
+param<UCP_CACHE_GPU_MAX_PARTITION_LOOKUP, ucp_cache_gpu_max_partition_lookup, int, 2>
+param<UCP_CACHE_GPU_DROP_PROBABILITY, ucp_cache_gpu_drop_probability, int, 50>
+param<UCP_CACHE_ACCESS_CONTROL, ucp_cache_access_control, int, 1>
+
+
+
+
+
 /* Cache coherence */
 param<ENABLE_CACHE_COHERENCE, enable_cache_coherence, bool, false>
 

src/cache_replacement/rrip.cc

@@ -0,0 +1,220 @@
+/**********************************************************************************************
+ * File         : rrip.cc
+ * Author       : Jaekyu Lee
+ * Date         : 04/26/2011 
+ * SVN          : $Id: cache.h,
+ * Description  : RRIP (Jaleel et al. ISCA 2010) 
+ *********************************************************************************************/
+
+
+#include <cmath>
+
+#include "rrip.h"
+#include "../cache.h"
+#include "../utils.h"
+#include "../debug_macros.h"
+#include "../all_knobs.h"
+#include "../statistics.h"
+
+#define DEBUG(args...) _DEBUG(*m_simBase->m_knobs->KNOB_DEBUG_CACHE_LIB, ## args)
+#define DEBUG_MEM(args...) _DEBUG(*m_simBase->m_knobs->KNOB_DEBUG_MEM_TRACE, ## args)
+
+
+// constructor
+
+// cache_rrip_c::cache_rrip_c(string name, int num_set, int assoc, int line_size, 
+//     int data_size, int bank_num, bool cache_by_pass, int core_id, Cache_Type cache_type_info, 
+//     bool enable_partition, macsim_c* simBase) : cache_c(name, num_set, assoc, line_size, 
+//       data_size, bank_num, cache_by_pass, core_id, cache_type_info, 1, 0, enable_partition, simBase)
+cache_rrip_c::cache_rrip_c(string name, int num_set, int assoc, int line_size, 
+    int data_size, int bank_num, bool cache_by_pass, int core_id, Cache_Type cache_type_info, 
+    bool enable_partition, int num_tiles, int interleave_factor, macsim_c* simBase) : cache_c(name, num_set, assoc, line_size, 
+      data_size, bank_num, cache_by_pass, core_id, cache_type_info, enable_partition, num_tiles,interleave_factor,simBase)
+{
+  int max_bit = *KNOB(KNOB_RRIP_CACHE_NUM_BIT);
+  m_max_lru_value   = static_cast<int>(pow(2, max_bit) - 1);
+  m_insertion_value = *m_simBase->m_knobs->KNOB_RRIP_CACHE_INSERT_AT;
+
+  // assume 32 sets for 1 SDM
+  m_modulo = num_set / 32;
+
+  m_sdm_counter = new int[m_max_application];
+  for (int ii = 0; ii < m_max_application; ++ii) {
+    m_sdm_counter[ii] = 0;
+//    m_total_miss[ii] = 0;
+  }
+
+  m_total_miss = new Counter[m_max_application];
+
+  m_sdm_max_counter_value = 
+    static_cast<int>(pow(2, static_cast<int>(*KNOB(KNOB_RRIP_CACHE_NUM_COUNTER_BIT))));
+
+  m_bip_epsilon = *m_simBase->m_knobs->KNOB_RRIP_CACHE_BIP_EPSILON;
+  m_access_count_by_type[2] = {0};
+  m_total_access_count = 0;
+  m_total_insert_count = 0;
+  m_access_ratio = 0.0;
+}
+
+
+// destructor
+cache_rrip_c::~cache_rrip_c()
+{
+}
+
+
+// find an entry to be replaced based on the policy
+cache_entry_c* cache_rrip_c::find_replacement_line(int set, int appl_id) 
+{
+//  bool gpuline = m_simBase->m_PCL->get_appl_type(appl_id);
+  bool gpuline = true;
+  int index = -1;
+  while (index == -1) {
+    for (int ii = 0; ii < m_assoc; ++ii) {
+      cache_entry_c* line = &(m_set[set]->m_entry[ii]);
+      // find invalid or 2^n-1 entry
+      if (line->m_valid != true || line->m_last_access_time == m_max_lru_value) {
+        index = ii;
+        break;
+      }
+    }
+
+
+    if (index == -1) {
+      int count = 0;
+      for (int ii = 0; ii < m_assoc; ++ii) {
+        cache_entry_c* line = &(m_set[set]->m_entry[ii]);
+        ++line->m_last_access_time;
+      }
+
+      if (count == 0) {
+        gpuline = !gpuline;
+      }
+    }
+  }
+
+  ++m_total_insert_count;
+
+  return &(m_set[set]->m_entry[index]);
+}
+
+
+// initialize a cache line
+void cache_rrip_c::initialize_cache_line(cache_entry_c *ins_line, Addr tag, Addr addr, 
+    int appl_id, bool gpuline, int set_id, bool skip) 
+{
+  ins_line->m_valid            = true;
+  ins_line->m_tag              = tag;
+  ins_line->m_base             = (addr & ~m_offset_mask);
+  ins_line->m_access_counter   = 0;
+  ins_line->m_pref             = false;
+  ins_line->m_appl_id          = appl_id;
+  ins_line->m_gpuline          = gpuline;
+  ins_line->m_skip             = skip;
+
+
+  // SRRIP
+  if (!*KNOB(KNOB_RRIP_CACHE_DYNAMIC_ON)) {
+    if (*KNOB(KNOB_RRIP_BIP_ALWAYS && gpuline)) {
+      // SRRIP
+      if (rand() % 100 < m_bip_epsilon) {
+        ins_line->m_last_access_time = m_insertion_value;
+      }
+      // LIP
+      else {
+        ins_line->m_last_access_time = m_max_lru_value;
+      }
+    }
+    else {
+      ins_line->m_last_access_time = m_insertion_value;
+    }
+  }
+  // DRRIP
+  else {
+    // BIMODAL
+    if (set_id % m_modulo == (appl_id * 2 + 1)) {
+      // SRRIP
+      if (rand() % 100 < m_bip_epsilon) {
+        ins_line->m_last_access_time = m_insertion_value;
+      }
+      // LIP
+      else {
+        ins_line->m_last_access_time = m_max_lru_value;
+      }
+    }
+    // SRRIP
+    else if (set_id % m_modulo == (appl_id * 2)) {
+      ins_line->m_last_access_time = m_insertion_value;
+    }
+    // Followers
+    else {
+      // SRRIP favor
+      if (m_sdm_counter[appl_id] <= 0) {
+        ins_line->m_last_access_time = m_insertion_value;
+      }
+      // BIMODAL
+      else {
+        // with small probability, insert it to original position (2n-2)
+        if (rand() % 100 < m_bip_epsilon) {
+          ins_line->m_last_access_time = m_insertion_value;
+        }
+        // LIP insertion (2n-1)
+        else {
+          ins_line->m_last_access_time = m_max_lru_value;
+        }
+      }
+    }
+  }
+
+
+  if (ins_line->m_gpuline) { 
+    ++m_num_gpu_line;
+    ++m_set[set_id]->m_num_gpu_line;
+  }
+  else {
+    ++m_num_cpu_line;
+    ++m_set[set_id]->m_num_cpu_line;
+  }
+}
+
+
+// update a line upon cache hits
+// use FP (Frequency Priority)
+void cache_rrip_c::update_line_on_hit(cache_entry_c* line, int set, int appl_id)
+{
+  if (line->m_last_access_time > 0) {
+//    --line->m_last_access_time;
+    line->m_last_access_time = 0;
+  }
+}
+
+
+
+
+void cache_rrip_c::update_cache_on_miss(int set_id, int appl_id)
+{
+  // DRRIP set dueling implementation
+  if (*KNOB(KNOB_RRIP_CACHE_DYNAMIC_ON)) {
+    m_total_miss[appl_id]++;
+    // SRRIP
+    if (set_id % m_modulo == (appl_id * 2)) {
+      ++m_sdm_counter[appl_id];
+      if (m_sdm_counter[appl_id] > m_sdm_max_counter_value) {
+        m_sdm_counter[appl_id] = m_sdm_max_counter_value;
+      }
+    }
+    // BIMODAL
+    else if (set_id % m_modulo == (appl_id * 2 + 1)) {
+      --m_sdm_counter[appl_id];
+      if (m_sdm_counter[appl_id] < -1 * m_sdm_max_counter_value) {
+        m_sdm_counter[appl_id] = m_sdm_max_counter_value * -1;
+      }
+    }
+  }
+}
+
+
+void cache_rrip_c::update_cache_on_access(Addr line_addr, int set, int appl_id)
+{
+  ++m_total_access_count;
+}

src/cache_replacement/rrip.h

@@ -0,0 +1,80 @@
+/**********************************************************************************************
+ * File         : rrip.h
+ * Author       : Jaekyu Lee
+ * Date         : 04/26/2011 
+ * SVN          : $Id: cache.h,
+ * Description  : RRIP (Jaleel et al. ISCA 2010) 
+ *********************************************************************************************/
+
+#ifndef RRIP_H
+#define RRIP_H
+
+#include "../cache.h"
+
+
+class cache_c;
+
+class cache_rrip_c : public cache_c
+{
+  public:
+    /**
+     * Constructor
+     */
+    //added num_tiles, interleave_factor  2024-03-26
+    cache_rrip_c(string name, int num_set, int assoc, int line_size, 
+        int data_size, int bank_num, bool cache_by_pass, int core_id, 
+        Cache_Type cache_type_info,  bool enable_partition, int num_tiles, int interleave_factor, macsim_c* simBase); 
+
+    /**
+     * Destructor
+     */
+    virtual ~cache_rrip_c();
+
+    /**
+     * fine a cache line to replace
+     * \param set set id
+     */
+    cache_entry_c * find_replacement_line(int set, int appl_id);
+
+    /**
+     * Initialize a new cache line
+     */
+    void initialize_cache_line(cache_entry_c *ins_line, Addr tag, Addr addr, int appl_id, 
+        bool gpuline, int set_id, bool skip);
+
+    /**
+     * Update LRU value on cache hit
+     */
+    void update_line_on_hit(cache_entry_c* line, int set, int appl_id);
+
+    /**
+     * Update cache on cache misses - for set dueling
+     */
+    void update_cache_on_miss(int set_id, int appl_id);
+
+    void update_cache_on_access(Addr tag, int set, int appl_id);
+
+  private:
+    /**
+     * Default constructor - do not implement
+     */
+    cache_rrip_c(); // do not implement
+
+    static const int m_max_application = 20;
+
+    int m_max_lru_value; /**< maximum lru value in RRIP */
+    int m_insertion_value; /**< lru value upon insertion */
+    int m_modulo; /**< modulo value for set monitorning */
+    int *m_sdm_counter;
+    Counter *m_total_miss;
+    //int *m_sdm_counter[m_max_application];
+    int m_sdm_max_counter_value;
+    int m_bip_epsilon;
+
+    int m_access_count_by_type[2];
+    Counter m_total_access_count;
+    Counter m_total_insert_count;
+    float m_access_ratio;
+};
+
+#endif