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FET simulator code cleanup
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Signed-off-by: Grzegorz Latosinski <[email protected]>
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glatosinski committed Nov 12, 2020
1 parent 07f30c4 commit 2aa2d14
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Showing 2 changed files with 24 additions and 17 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -18,42 +18,48 @@
# SPDX-License-Identifier: Apache-2.0

import PySpice.Logging.Logging as Logging
logger = Logging.setup_logging()
from PySpice.Spice.Netlist import Circuit
from PySpice.Unit import *
from PySpice.Unit import u_V
import matplotlib.pyplot as plt
from pathlib import Path
import csv

logger = Logging.setup_logging()


def create_test_circuit(fet_type, iparam, fet_L, fet_W, corner_path):
c=Circuit('gm_id')
c = Circuit('gm_id')
c.include(corner_path)

# create the circuit
c.V('gg', 1, c.gnd, 0@u_V)
c.V('dd', 2, c.gnd, 1.8@u_V)
c.X('M1', fet_type, 2, 1, c.gnd, c.gnd, L=fet_L, W=fet_W, ad="'W*0.29'",
pd="'2*(W+0.29)'", as_="'W*0.29'", ps="'2*(W+0.29)'", nrd="'0.29/W'",
c.X(
'M1', fet_type, 2, 1, c.gnd, c.gnd, L=fet_L, W=fet_W, ad="'W*0.29'",
pd="'2*(W+0.29)'", as_="'W*0.29'", ps="'2*(W+0.29)'", nrd="'0.29/W'",
nrs="'0.29/W'", sa=0, sb=0, sd=0, nf=1, mult=1
)
return c
return c


def run_sim(c, iparam, fet_W):
sim = c.simulator()
sim.save_internal_parameters(
iparam%'gm', iparam%'id', iparam%'gds', iparam%'cgg'
iparam % 'gm', iparam % 'id', iparam % 'gds', iparam % 'cgg'
)

# run the dc simulation
an = sim.dc(Vgg=slice(0, 1.8, 0.01))

# calculate needed values..need as_ndarray() since most of these have None as the unit and that causes an error
gm_id = an.internal_parameters[iparam%'gm'].as_ndarray() / an.internal_parameters[iparam%'id'].as_ndarray()
ft = an.internal_parameters[iparam%'gm'].as_ndarray() / an.internal_parameters[iparam%'cgg'].as_ndarray()
id_W = an.internal_parameters[iparam%'id'].as_ndarray() / fet_W
gm_gds = an.internal_parameters[iparam%'gm'].as_ndarray() / an.internal_parameters[iparam%'gds'].as_ndarray()
# calculate needed values..need as_ndarray() since most of these have None
# as the unit and that causes an error
gm_id = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
an.internal_parameters[iparam % 'id'].as_ndarray())
ft = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
an.internal_parameters[iparam % 'cgg'].as_ndarray())
id_W = (an.internal_parameters[iparam % 'id'].as_ndarray() / fet_W)
gm_gds = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
an.internal_parameters[iparam % 'gds'].as_ndarray())

return gm_id, ft, id_W, gm_gds, an.nodes['v-sweep']

Expand Down Expand Up @@ -101,8 +107,9 @@ def generate_fet_plots(
outdir,
outprefix,
only_W=None,
ext='png'):
print(f'[generate_fet_plots] {fet_type} {corner_path} {bins_csv} {outdir} {outprefix} {only_W}')
ext='svg'):
print(f'[generate_fet_plots] {fet_type} {corner_path} {bins_csv}' +
f'{outdir} {outprefix} {only_W}')
iparam = f'@m.xm1.m{fet_type}[%s]'
# fet_W and fet_L values here are only for initialization, they are
# later changed in the for loop
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Expand Up @@ -48,7 +48,7 @@
['nfet_03v3_nvt-and-nfet_05v0_nvt', 'nfet_03v3_nvt', None],
['nfet_05v0_nvt', 'nfet_05v0_nvt', None],
# ['nfet_20v0'], TODO provide
# ['nfet_20v0_iso', 'nfet_20v0_nvt_iso', None], TODO invalid bins.csv file
# ['nfet_20v0_iso', 'nfet_20v0_nvt_iso', None], TODO invalid bins.csv
# ['nfet_20v0_nvt', 'nfet_20v0_nvt', None], TODO invalid bins.csv file
# ['nfet_20v0_zvt', 'nfet_20v0_zvt', None], TODO invalid bins.csv file
# ['nfet_g11v0d16v0'], TODO provide
Expand All @@ -65,8 +65,8 @@
generate_fet_plots(
f'sky130_fd_pr__{fetname}',
typicalcorner,
args.fd_pr_dir / f'cells/{fetname}/sky130_fd_pr__{fetname}.bins.csv',
args.device_details_dir / outdir,
args.fd_pr_dir/f'cells/{fetname}/sky130_fd_pr__{fetname}.bins.csv',
args.device_details_dir/outdir,
f'sim_{fetname}_',
onlyw
)

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