flatten: add -insertbarriers flag

* This uses $barrier optimization barriers to connect wires into the
  flattened module instead of connections

passes/techmap/flatten.cc

@@ -60,6 +60,7 @@ struct FlattenWorker
 	bool ignore_wb = false;
 	bool create_scopeinfo = true;
 	bool create_scopename = false;
+	bool insert_barriers = false;
 
 	template<class T>
 	void map_attributes(RTLIL::Cell *cell, T *object, IdString orig_object_name)
@@ -246,7 +247,11 @@ struct FlattenWorker
 				log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n",
 					log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second));
 
-			module->connect(new_conn);
+			if (insert_barriers)
+				module->addBarrier(NEW_ID, new_conn.second, new_conn.first);
+			else
+				module->connect(new_conn);
+
 			sigmap.add(new_conn.first, new_conn.second);
 		}
 
@@ -345,6 +350,11 @@ struct FlattenPass : public Pass {
 		log("        with a public name the enclosing scope can be found via their\n");
 		log("        'hdlname' attribute.\n");
 		log("\n");
+		log("    -insertbarriers\n");
+		log("        Use $barrier cells to connect flattened modules to their surrounding\n");
+		log("        scope instead of connections. This prevents optimization passes\n");
+		log("        optimizing through the connection.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -367,6 +377,10 @@ struct FlattenPass : public Pass {
 				worker.create_scopename = true;
 				continue;
 			}
+			if (args[argidx] == "-insertbarriers") {
+				worker.insert_barriers = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);