Add stm32wb soc family (outpost-os#114)

.github/workflows/gnulinux.yml

@@ -29,11 +29,11 @@ jobs:
           if "${{ github.event_name }}" == "pull_request":
             operating_system = [ 'mesonbuild/ubuntu-rolling', 'mesonbuild/arch:latest' ]
             toolchain = [ 'gcc|12.3.Rel1', 'gcc|10.3-2021.07', 'gcc|13.2.Rel1' ]
-            config = [ 'nucleo_u5a5_autotest', 'nucleo_u5a5_nooutput', 'stm32f429i_disc1_debug', 'stm32f429i_disc1_release', 'stm32f429i_disc1_autotest' ]
+            config = [ 'nucleo_u5a5_autotest', 'nucleo_wb55_autotest', 'nucleo_u5a5_nooutput', 'stm32f429i_disc1_debug', 'stm32f429i_disc1_release', 'stm32f429i_disc1_autotest' ]
           else:
             operating_system = [ 'mesonbuild/ubuntu-rolling' ]
             toolchain = [ 'gcc|12.3.Rel1' ]
-            config = [ 'nucleo_u5a5_autotest', 'stm32f429i_disc1_debug', 'nucleo_l476rg_debug', 'nucleo_f401re' ]
+            config = [ 'nucleo_u5a5_autotest', 'nucleo_wb55_autotest', 'stm32f429i_disc1_debug', 'nucleo_l476rg_debug', 'nucleo_f401re' ]
           with open(os.environ['GITHUB_OUTPUT'], 'w') as gh_out:
             gh_out.write(f"operating_system={operating_system}\n")
             gh_out.write(f"toolchain={toolchain}\n")

configs/nucleo_wb55_autotest_defconfig

@@ -0,0 +1,8 @@
+# SPDX-FileCopyrightText: 2025 Ledger SAS
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARCH_MCU_STM32WB55_CM4=y
+CONFIG_DRV_STM32_LPUART=y
+CONFIG_STANDALONE_MODE=y
+CONFIG_BUILD_TARGET_AUTOTEST=y
+# CONFIG_TEST_SHM is not set

dts/examples/nucleo_wb55_autotest.dts

@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2025 Ledger SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <st/wb/stm32wb55Xg.dtsi>
+#include <dt-bindings/pinctrl/stm32-pinctrl.h>
+#include <sentry.dtsi>
+
+/{
+	chosen {
+		sentry,debug_stdout = <&lpuart1>;
+		sentry,autotestram_section = <&autotest_ram>;
+		sentry,autotestcode_section = <&autotest_code>;
+	};
+};
+
+/{
+	reserved-memory {
+		autotest_code: autotest_code@800d000 {
+			reg = <0x8010000 0xe000>;
+			compatible = "outpost,memory-pool";
+		};
+
+		autotest_ram: autotest_memory@20008000 {
+			reg = <0x20008000 0x1000>;
+			compatible = "outpost,memory-pool";
+		};
+    };
+};
+
+&flash0 {
+	reg = <0x08000000 DT_SIZE_M(1)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(192)>;
+};
+
+
+&flash {
+	wait-state = <3>; /* According to voltage supply and sysclock */
+	status = "okay";
+};
+
+&clk_lsi1 {
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&clk_hsi48 {
+	status = "okay";
+};
+
+&clk_msi {
+	status = "okay";
+};
+
+&pll {
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(64)>;
+	bus-prescalers = <0>, <0>, <0>;
+	bus-names = "ahb", "apb1", "apb2";
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&gpioe {
+	status = "okay";
+};
+
+&exti {
+	events = <49>;
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&syscfg {
+	status = "okay";
+};
+
+&lpuart1{
+	status = "okay";
+	pinctrl-0 = <&lpuart1_tx>, <&lpuart1_rx>;
+};
+
+&pinctrl {
+	lpuart1_tx: lpuart1_tx  {
+		pinmux = <&gpioa 2 STM32_DT_PIN_MODE_ALTFUNC(8)>;
+		pincfg = <STM32_OTYPER_PUSH_PULL \
+				  STM32_OSPEEDR_VERY_HIGH_SPEED \
+				  STM32_PUPDR_NO_PULL>;
+	};
+
+	lpuart1_rx: lpuart1_rx  {
+		pinmux = <&gpioa 3 STM32_DT_PIN_MODE_ALTFUNC(8)>;
+		pincfg = <STM32_OTYPER_PUSH_PULL \
+				  STM32_OSPEEDR_VERY_HIGH_SPEED \
+				  STM32_PUPDR_NO_PULL>;
+	};
+};

kernel/include/bsp/drivers/clk/pwr.h

@@ -65,6 +65,16 @@ typedef enum clk_vos_scale {
       s == POWER_VOS_SCALE_2 ||
       s == POWER_VOS_SCALE_1;
 */
+#elif defined(CONFIG_SOC_SUBFAMILY_STM32WB)
+typedef enum clk_vos_scale {
+    POWER_VOS_SCALE_1   = 0x1UL,
+    POWER_VOS_SCALE_2   = 0x2UL,
+} clk_vos_scale_t;
+/*@
+    predicate scale_is_valid(uint8_t s) =
+      s == POWER_VOS_SCALE_2 ||
+      s == POWER_VOS_SCALE_1;
+*/
 #endif
 kstatus_t pwr_probe(void);
 

kernel/include/sentry/arch/asm-cortex-m/meson.build

@@ -61,6 +61,8 @@ buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32L4', if_true: files('stm32l4
 # see: https://git.orange.ledgerlabs.net/outpost/sentry-kernel/issues/188
 # rework this as this is weak
 buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32U5', if_true: files('stm32l4-buses.h.in'))
+buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32WB', if_true: files('stm32l4-buses.h.in'))
+
 # here, we can add other templates for other ARM SoC famillies if needed
 buses_h_in_set_config = buses_h_in_set.apply(kconfig_data, strict: false)
 

kernel/src/arch/asm-cortex-m/Kconfig

@@ -166,6 +166,7 @@ config SOC_SUBFAMILY_STM32WB
 	select SOC_FAMILY_STM32
 	select HAS_FPU
 	select HAS_MPU
+	select HAS_RNG
 	select HAS_MPU_PMSA_V7
 	# Cache support ?
 	help
@@ -218,7 +219,7 @@ config ARCH_ARM_CORTEX_NAME
 
 config ARCH_SOCNAME
 	string
-	default "STM32WB55" if ARCH_MCU_STM32WB55
+	default "STM32WB55_CM4" if ARCH_MCU_STM32WB55_CM4
 	default "STM32F401" if ARCH_MCU_STM32F401
 	default "STM32F407" if ARCH_MCU_STM32F407
 	default "STM32F419" if ARCH_MCU_STM32F419
@@ -259,7 +260,7 @@ config ARCH_MCU_STM32F401
 	bool "STM32F401"
 	select SOC_SUBFAMILY_STM32F4
 
-config ARCH_MCU_STM32WB55
+config ARCH_MCU_STM32WB55_CM4
 	bool "STM32WB55"
 	select SOC_SUBFAMILY_STM32WB
 

kernel/src/drivers/clk/meson.build

@@ -146,6 +146,21 @@ stm32u5_rcc_h = dtsgen.process(
 bsp_clk_private_gen_header_set.add(stm32u5_rcc_h)
 endif
 
+if kconfig_data.get('CONFIG_SOC_SUBFAMILY_STM32WB', 0) == 1
+stm32wb_rcc_c_template = files('stm32wb-rcc.c.in')
+stm32wb_rcc_c = dtsgen.process(
+    stm32wb_rcc_c_template,
+    preserve_path_from: meson.current_source_dir(),
+)
+bsp_clk_private_gen_source_set.add(stm32wb_rcc_c)
+stm32wb_rcc_h_template = files('stm32wb-rcc.h.in')
+stm32wb_rcc_h = dtsgen.process(
+    stm32wb_rcc_h_template,
+    preserve_path_from: meson.current_source_dir(),
+)
+bsp_clk_private_gen_header_set.add(stm32wb_rcc_h)
+endif
+
 pwr_h = custom_target('gen_pwr',
     input: peripheral_defs_in,
     output: '@0@_defs.h'.format('pwr'),

kernel/src/drivers/clk/stm32-pwr.c

@@ -19,7 +19,7 @@
 #include "pwr_defs.h"
 
 /* TODO: move stm32l4/f4 in a dedicated file */
-#if defined(CONFIG_SOC_SUBFAMILY_STM32L4)
+#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32WB)
 #define PWR_CR_REG PWR_CR1_REG
 #define PWR_CR_VOS_MASK PWR_CR1_VOS_MASK
 #define PWR_CR_VOS_SHIFT PWR_CR1_VOS_SHIFT
@@ -28,7 +28,7 @@
 #endif
 
 /* FIXME */
-#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32F4)
+#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32F4) || defined(CONFIG_SOC_SUBFAMILY_STM32WB)
 # if defined(CONFIG_ARCH_MCU_STM32F401)
 #  define DEFAULT_SCALE_MODE POWER_VOS_SCALE_2
 # else
@@ -59,7 +59,7 @@ kstatus_t pwr_probe(void)
     return pwr_set_voltage_regulator_scaling(DEFAULT_SCALE_MODE);
 }
 
-#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32F4)
+#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32F4) || defined(CONFIG_SOC_SUBFAMILY_STM32WB)
 /*@
     requires scale_is_valid(scale);
     ensures \result == K_STATUS_OKAY;

kernel/src/drivers/clk/stm32-rcc.c.in

@@ -31,6 +31,8 @@
 #include "stm32l4-rcc.h"
 #elif defined(CONFIG_SOC_SUBFAMILY_STM32U5)
 #include "stm32u5-rcc.h"
+#elif defined(CONFIG_SOC_SUBFAMILY_STM32WB)
+#include "stm32wb-rcc.h"
 #endif
 
 #include "stm32-rcc.h"
@@ -333,10 +335,18 @@ __STATIC_INLINE size_t rcc_get_register(bus_id_t busid, rcc_opts_t flags)
         reg_base = RCC_BASE_ADDR;
     }
 
+/* XXX:
+ *  As bus ID comes from DTS and this test function is based on DTS too
+ *  One can assume that this is consistent.
+ * TODO:
+ *  To be refined
+ */
+#if 0
     if (unlikely(!BUS_IS_VALID(busid))) {
         /* FIXME: status (error) should be returned instead */
-        return 0;
+        // return 0;
     }
+#endif
     /*@ assert bus_is_valid(busid); */
     reg_base += busid;
 
@@ -369,9 +379,17 @@ kstatus_t rcc_enable(bus_id_t busid, uint32_t clk_msk, rcc_opts_t flags)
         goto err;
     }
 
+/* XXX:
+ *  As bus ID comes from DTS and this test function is based on DTS too
+ *  One can assume that this is consistent.
+ * TODO:
+ *  To be refined
+ */
+#if 0
     if (unlikely(!BUS_IS_VALID(busid))) {
         goto err;
     }
+#endif
     /*@ assert bus_is_valid(busid); */
     size_t reg_base = rcc_get_register(busid, flags);
 
@@ -453,6 +471,9 @@ kstatus_t rcc_get_bus_clock(bus_id_t busid, uint32_t *busclk)
     /*@ assert bus_is_valid(busid); */
     switch (busid) {
         case BUS_APB1:
+#if defined(HAS_BUS_APB1_2)
+        case BUS_APB1 + 4:
+#endif
             *busclk = RCC_APB1_CLOCK_FREQUENCY;
             break;
         case BUS_APB2:
@@ -466,6 +487,9 @@ kstatus_t rcc_get_bus_clock(bus_id_t busid, uint32_t *busclk)
         case BUS_AHB1:
 #if defined(HAS_BUS_AHB2)
         case BUS_AHB2:
+#if defined(HAS_BUS_AHB2_2)
+        case BUS_AHB2 + 4:
+#endif
 #endif
 #if defined(HAS_BUS_AHB3)
         case BUS_AHB3:

kernel/src/drivers/clk/stm32l4-rcc.h.in

@@ -81,6 +81,8 @@
 #define RCC_HSI48RDY RCC_CRRCR_HSI48RDY
 #endif
 
+#define HAS_BUS_APB1_2
+
 {#- There is only one main PLL for stm32f4xx families #}
 {%- set pll = dts.get_compatible("st,stm32l4xx-pll")[0] %}
 {%- if pll is not none and pll.status == "okay"%}

kernel/src/drivers/clk/stm32u5-rcc.h.in

@@ -57,6 +57,9 @@
 #define RCC_HSI48ON RCC_CR_HSI48ON
 #define RCC_HSI48RDY RCC_CR_HSI48RDY
 
+#define HAS_BUS_APB1_2
+#define HAS_BUS_AHB2_2
+
 typedef enum stm32u5_pll_id {
     PLL_ID_1 = 0,
     PLL_ID_2 = 1,