added a comment on test jiig setup

fpga-logi · Mar 12, 2015 · adf3f67 · adf3f67
1 parent c17ba39
commit adf3f67
Showing 1 changed file with 25 additions and 0 deletions.
diff --git a/logi-test/sw/common/config.h b/logi-test/sw/common/config.h
@@ -1,3 +1,28 @@
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+/*
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+PMOD Diagram
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+vcc gnd 3 2 1 0
+vcc gnd 7 6 5 4
+
+test jiig for PMOD test shorts upper row pins with lower row pins one by one :
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+- 0 & 4 are shorted
+- 1 & 5 are shorted
+- 2 & 6 are shorted
+- 3 & 7 are shorted
+
+*/
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+
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 //DEFINE WHICH TESTS TO RUN
 //COMMENT OUT TESTS YOU DO NOT WANT TO RUN
 #define TEST_SDRAM 		//test the SDRAM