changing teh ucf to add pull-ups

fpga-logi · Mar 12, 2015 · 38bd190 · 38bd190
1 parent 682234e
commit 38bd190
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Showing 3 changed files with 15 additions and 15 deletions.
diff --git a/logi-test/hw/logipi/hdl/logipi_r1_5.ucf b/logi-test/hw/logipi/hdl/logipi_r1_5.ucf
@@ -76,17 +76,17 @@ NET "SDRAM_DQ<14>" 		LOC = "P56"			| IOSTANDARD = LVTTL ;
 NET "SDRAM_DQ<15>"		LOC = "P55"			| IOSTANDARD = LVTTL ;
 
 #PMOD1#############################################################################
-NET "PMOD1<0>" 			LOC = "P5" 			| IOSTANDARD = LVTTL;
-NET "PMOD1<1>" 			LOC = "P2" 			| IOSTANDARD = LVTTL;
-NET "PMOD1<2>" 			LOC = "P1" 			| IOSTANDARD = LVTTL;
-NET "PMOD1<3>" 			LOC = "P16" 		| IOSTANDARD = LVTTL;
-NET "PMOD1<4>"				LOC = "P88" 		| IOSTANDARD = LVTTL;
-NET "PMOD1<5>" 			LOC = "P92" 		| IOSTANDARD = LVTTL;
-NET "PMOD1<6>" 			LOC = "P93" 		| IOSTANDARD = LVTTL;
-NET "PMOD1<7>" 			LOC = "P94" 		| IOSTANDARD = LVTTL;
+NET "PMOD1<0>" 			LOC = "P5" 			| IOSTANDARD = LVTTL | PULLUP;
+NET "PMOD1<1>" 			LOC = "P2" 			| IOSTANDARD = LVTTL | PULLUP;
+NET "PMOD1<2>" 			LOC = "P1" 			| IOSTANDARD = LVTTL | PULLUP;
+NET "PMOD1<3>" 			LOC = "P16" 		| IOSTANDARD = LVTTL | PULLUP;
+NET "PMOD1<4>"				LOC = "P88" 		| IOSTANDARD = LVTTL | PULLUP;
+NET "PMOD1<5>" 			LOC = "P92" 		| IOSTANDARD = LVTTL | PULLUP;
+NET "PMOD1<6>" 			LOC = "P93" 		| IOSTANDARD = LVTTL | PULLUP;
+NET "PMOD1<7>" 			LOC = "P94" 		| IOSTANDARD = LVTTL | PULLUP;
 #PMOD2#############################################################################
-NET "PMOD2<0>" 			LOC = "P142" 		| IOSTANDARD = LVTTL;
-NET "PMOD2<1>" 			LOC = "P141" 		| IOSTANDARD = LVTTL;
+NET "PMOD2<0>" 			LOC = "P142" 		| IOSTANDARD = LVTTL | PULLUP;
+NET "PMOD2<1>" 			LOC = "P141" 		| IOSTANDARD = LVTTL | PULLUP;
 NET "PMOD2<2>" 			LOC = "P15" 		| IOSTANDARD = LVTTL;
 NET "PMOD2<3>" 			LOC = "P14" 		| IOSTANDARD = LVTTL;
 NET "PMOD2<4>" 			LOC = "P144" 		| IOSTANDARD = LVTTL;

diff --git a/logi-test/hw/logipi/ise/ipcore_dir/clock_gen.xise b/logi-test/hw/logipi/ise/ipcore_dir/clock_gen.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="clock_gen/example_design/clock_gen_exdes.ucf" xil_pn:type="FILE_UCF"/>

diff --git a/logi-test/hw/logipi/ise/logipi_test.xise b/logi-test/hw/logipi/ise/logipi_test.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="../../../../../logi-hard/hdl/wishbone/spi_wishbone_wrapper.vhd" xil_pn:type="FILE_VHDL">
@@ -104,7 +104,7 @@
     <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>