opcodes: Reflect register name change for ARCv3 #74
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The previous "arc*-..." pattern was very permissive. Now there is only "arc-..." and "arceb-..." patterns.
Introduce an "ARC_ISA_NONE = 0" to "arc_isa" enum in order to reflect an invalid value. Not that it really matters but this tweak does not alter the other enum values.
This is the arc64 gdb suited to debug baremetal programs
served through a gdbstub (openocd,qemu,etc.). To build:
$ configure --target=arc64-elf \
--with-pkgversion="arc64 baremetal" \
--with-endian=little \
--enable-languages=c,c++ \
--prefix=/path/to/install \
--enable-shared \
--with-gnu-as \
--with-gnu-ld \
--without-newlib \
--disable-libgomp \
--disable-ld \
--disable-gas \
--disable-binutils
The newly introduced arc64-newlib-tdep.c file uses bfd_arch_arc64 and the correct offset for PC in jumpbuffer (17). Moreover, the arc64-tdep.c also uses bfd_arch_arc64 now.
This is the cross platform gdb suited to debug arc64 linux
programs served with arc64 gdbserver. To build:
$ configure --target=arc64-linux \
--with-pkgversion="arc64 linux gnu" \
--with-endian=little \
--enable-languages=c,c++ \
--prefix=/path/to/install \
--enable-shared \
--with-gnu-as \
--with-gnu-ld \
--without-newlib \
--disable-libgomp \
--disable-ld \
--disable-gas \
--disable-binutils
This gdbserver is suited for running inside arc64 linux while
serving to a cross arc64-linux gdb. To build:
$ module load <arcv3-toolchain>
$ configure --host=arc64-linux-gnu \
--prefix=/usr \
--disable-build-with-cxx \
--disable-ld \
--disable-gas \
--disable-binutils \
--disable-gdb
This is the cross platform gdb suited to debug arc32 linux
programs served with arc32 gdbserver. To build:
$ configure --target=arc32-linux \
--with-pkgversion="arc32 linux gnu" \
--with-endian=little \
--enable-languages=c,c++ \
--prefix=/path/to/install \
--enable-shared \
--with-gnu-as \
--with-gnu-ld \
--without-newlib \
--disable-libgomp \
--disable-ld \
--disable-gas \
--disable-binutils
This gdbserver is suited for running inside arc32 linux while
serving to a cross arc32-linux gdb. To build:
$ module load <arcv3-toolchain>
$ configure --host=arc32-linux-gnu \
--prefix=/usr \
--disable-build-with-cxx \
--disable-ld \
--disable-gas \
--disable-binutils \
--disable-gdb
The disassembler can recognize the alternative register names ILINK1 and ILINK2. Update tests. gas/testsuite/gas/arc xxxx-xx-xx Claudiu Zissulescu <[email protected]> * gas/testsuite/gas/arc/adc.d: Update ILINK1/INLINK2 reg names. * gas/testsuite/gas/arc/add.d: Likewise. * gas/testsuite/gas/arc/and.d: Likewise. * gas/testsuite/gas/arc/asl.d: Likewise. * gas/testsuite/gas/arc/asr.d: Likewise. * gas/testsuite/gas/arc/bic.d: Likewise. * gas/testsuite/gas/arc/lsr.d: Likewise. * gas/testsuite/gas/arc/nps400-1.d: Likewise. * gas/testsuite/gas/arc/or.d: Likewise. * gas/testsuite/gas/arc/ror.d: Likewise. * gas/testsuite/gas/arc/sbc.d: Likewise. * gas/testsuite/gas/arc/sub.d: Likewise. * gas/testsuite/gas/arc/textinsn3op.d: Likewise. * gas/testsuite/gas/arc/warn.exp: Update predicate. * gas/testsuite/gas/arc/arc.exp: Likewise. Signed-off-by: Claudiu Zissulescu <[email protected]>
binutils/testsuite/binutils-all xxxx-xx-xx Claudiu Zissulescu <[email protected]> * binutils/testsuite/binutils-all/arc/objdump.exp: Update predicate. Signed-off-by: Claudiu Zissulescu <[email protected]>
Update Synopsys ARC64 machine name fileds, update readelf to dump correctly ARC64 relocations. binutils: xxxx-xx-xx Claudiu Zissulescu <[email protected]> * bintuils/readelf.c (guess_is_rela): Recognize ARC64 new machines. (dump_relocations): Likewise. (get_section_type_name): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_16bit_abs_reloc): Likewise. (is_none_reloc): Likewise. (process_arch_specific): Likewise. (get_machine_flags): Likewise. (get_machine_name): Update ARC64's name. Signed-off-by: Claudiu Zissulescu <[email protected]>
gas/ xxxx-xx-xx Claudiu Zissulescu <[email protected]> * gas/testsuite/gas/arc64/arc64.exp: New file. * gas/testsuite/gas/arc64/float01.d: Likewise. * gas/testsuite/gas/arc64/float01.s: Likewise. * gas/testsuite/gas/arc64/ldd.d: Likewise. * gas/testsuite/gas/arc64/ldd.s: Likewise. * gas/testsuite/gas/arc64/lddl.d: Likewise. * gas/testsuite/gas/arc64/lddl.s: Likewise. * gas/testsuite/gas/arc64/load.d: Likewise. * gas/testsuite/gas/arc64/load.s: Likewise. * gas/testsuite/gas/arc64/st.d: Likewise. * gas/testsuite/gas/arc64/st.s: Likewise. * gas/testsuite/gas/arc64/std.d: Likewise. * gas/testsuite/gas/arc64/std.s: Likewise. * gas/testsuite/gas/arc64/stdl.d: Likewise. * gas/testsuite/gas/arc64/stdl.s: Likewise. * gas/testsuite/gas/arc64/stl.d: Likewise. * gas/testsuite/gas/arc64/stl.s: Likewise. Signed-off-by: Claudiu Zissulescu <[email protected]>
ld/ xxxx-xx-xx Claudiu Zissulescu <[email protected]> * ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd: New file. * ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd: Likewise. * ld/testsuite/ld-arc64/arcv3_64-reloc-near.s: Likewise. * ld/testsuite/ld-arc64/arcv3_64.exp: Likewise. * ld/testsuite/ld-arc64/bl34.dd: Likewise. * ld/testsuite/ld-arc64/bl34.s: Likewise. * ld/testsuite/ld-arc64/linkscript.ld: Likewise. * ld/testsuite/ld-arc64/plt34-got.dd: Likewise. * ld/testsuite/ld-arc64/plt34-got.s: Likewise. * ld/testsuite/ld-arc64/plt34-reloc.dd: Likewise. * ld/testsuite/ld-arc64/plt34-reloc.s: Likewise. Signed-off-by: Claudiu Zissulescu <[email protected]>
The new Synopsys's ARC64 architecture is capable to run either 64-bit ISA or 32-bit ISA. The new 32-bit ISA is not compatible with the old Synopsys ARCv1/ARCv2 ISA, however, it retains a lot of common concepts. Thus, this patch is reusing the old ARC BFD backend and adds the necessary bits for the new architecture in a similar way as it is done for RISCV backend. bfd/ xxxx-xx-xx Claudiu Zissulescu <[email protected]> * bfd/Makefile.am: Add ARC64 files. * bfd/Makefile.in: Regerate. * bfd/arc-got.h (TCB_SIZE): Depends on the target architecture. (GOT_ENTRY_SIZE): New define. (write_in_got): Likewise. (read_from_got): Likewise. (align_power): Likewise. (arc_got_entry_type_for_reloc): Use RELA_SIZE and GOT_ENTRY_SIZE. (arc_fill_got_info_for_reloc): Update formating. (relocate_fix_got_relocs_for_got_info): Likewise. (arc_static_sym_data): Deleted structure. (get_static_sym_data): Deleted function. (relocate_fix_got_relocs_for_got_info): Use symbol static data. (create_got_dynrelocs_for_single_entry): Update formating. (create_got_dynrelocs_for_got_info): Likewise. * bfd/arc-plt.c: New file. * bfd/arc-plt.def: Add ARC64 PLT entry. * bfd/arc-plt.h: Clean it up, move functionality to arc-plt.c file. * bfd/archures.c: Add ARC64 target. * bfd/config.bfd: Likewise. * bfd/configure.ac: Likewise. * bfd/bfd-in2.h: Regenerate. * bfd/configure: Likewise. * bfd/libbfd.h: Likewise. * bfd/cpu-arc.c: Clean it up. * bfd/cpu-arc64.c: New file. * bfd/elf32-arc.c: Renamed to elfnn-arc.c. * bfd/elfnn-arc.c: New file. * bfd/reloc.c: Add new ARC64 relocs. * bfd/targets.c: Add ARC64 target. Signed-off-by: Claudiu Zissulescu <[email protected]> add patch 8
Add ARC64's linker bits. ld/ xxxx-xx-xx Claudiu Zissulescu <[email protected]> * ld/Makefile.am: Add ARC64 targets. * ld/configure.tgt: Likewise. * ld/Makefile.in: Regenerate. * ld/emulparams/arc64elf32.sh: New file. * ld/emulparams/arc64elf64.sh: Likewise. * ld/emulparams/arc64linux32.sh: Likewise. * ld/emulparams/arc64linux64.sh: Likewise. * ld/scripttempl/elfarc.sc: Add noinit, update stack and heap definitions. * ld/testsuite/ld-arc/got-weak.d: Deleted file. * ld/testsuite/ld-arc/got-weak.s: Likewise. Signed-off-by: Claudiu Zissulescu <[email protected]>
include/ xxxx-xx-xx Claudiu Zissulescu <[email protected]> * include/elf/arc-cpu.def: Add new HS5x and HS6x CPUs. * include/elf/arc-reloc.def: Add new ARC64 relocations. * include/elf/arc.h (EF_ARC_CPU_ARC64): New define. * include/opcode/arc-attrs.h (FEATURE_LIST_NAME): Update predicate. * include/opcode/arc-func.h: Update formating. (replace_disp8ls): New function. (replace_disp9s): Likewise. (replace_disp6s): Likewise. (replace_disp7s): Likewise. (replace_disp12s): Likewise. * include/opcode/arc.h (ARC_OPCODE_ARC64): New define. (ARC_OPCODE_ARC32): Likewise. (ARC_OPERAND_FP): Likewise. (HARD_FIELDF): Likewise. (ARC_OPCODE_ARCVx): New macro. (arc_flag_class): Update structure to hold new extract/insert functions for flags. (INSN3OP): Update macro. (FP_SIZE, TPOF, DPOF, SOPF, COPF, CONVOPS): New enums. Signed-off-by: Claudiu Zissulescu <[email protected]>
The new Synopsys ARC64 processor has a similar instruction format like the old ARCv1 and ARCv2 ISA. Thus, the ARC64 addition is using whatever we have for old ARC processors plus some ARC64 spcific mods. gas/ xxxx-xx-xx Claudiu Zissulescu <[email protected]> * gas/config/tc-arc.h: Selectively define default target macros. * gas/configure.ac: Add ARC64 target. * gas/configure.tgt: Likewise. * gas/configure: Regenerate * gas/config.in: Regenerate. * gas/config/tc-arc.c (DEFAULT_ARCH): New macro. (default_arch): New variable. (md_pseudo_table): Add xword. (md_shortopts): Only a few options are recognized by the new ARC64 assembler. (md_longopts): Likewise. (ARC_CPU_TYPE_A64x): New define. (ARC_CPU_TYPE_A32x): Likewise. (cpu_type): New arch field. (selected_cpu): Update fields. (arc_opcode_hash_entry_iterator_init): Formating. (arc_opcode_hash_entry_iterator_next): Likewise. (arc_select_cpu): Likewise. (arc_option): Likewise. (check_cpu_feature): Likewise. (debug_exp): Recognize new expression operands. (parse_reloc_symbol): Parse new signed/unsigend cases. (parse_opcode_flags): Update for the case when the flags needs insert/extract functions. (find_opcode_match): Match new signed/unsigned 32-bit immediates. (autodetect_attributes): PLT34 only available for ARC64. (md_assemble): Extend match characters. (declare_fp_set): New function. (init_default_arch): Likewise. (md_begin): Detect and initialize the correct CPU and coresponding registers. (md_pcrel_from_section): Add new relocs. (arc_target_format): New function. (md_apply_fix): Add new relocs. (md_parse_option): Update options. (arc_show_cpu_list): Update with ARC64 cpus. (md_show_usage): Update messages. (may_relax_expr): Add PLT34 case. (assemble_insn): Update for ARC64. (arc_make_nops): New function. (arc_handle_align): Refurbish this function, use arc_make_nops. (tc_arc_fix_adjustable): Update messages. Signed-off-by: Claudiu Zissulescu <[email protected]> add patch 11
opcodes/ xxxx-xx-xx Claudiu Zissulescu <[email protected]> * opcodes/arc64-tbl.h: New file. Signed-off-by: Claudiu Zissulescu <[email protected]>
opcodes/ xxxx-xx-xx Claudiu Zissulescu <[email protected]> * opcodes/Makefile.am: Add ARC64 opcode file. * opcodes/Makefile.in: Regenerate. * opcodes/arc-opc.c: Move the common functionality to arcxx-opc.inc. Keep only ARCv2 ARCv1 specifics. * opcodes/arc-ext-tbl.h: Deleted file. * opcodes/arcxx-opc.inc: New file. * opcodes/arc64-opc.c: Likewise. * opcodes/arc-fxi.h (insert_uimm9_a32_11_s): New function. (extract_uimm9_a32_11_s): Likewise. (insert_uimm10_13_s): Likewise. (extract_uimm10_13_s): Likewise. * opcodes/configure: Regenerate. * opcodes/configure.ac: Add ARC64 target. * opcodes/disassemble.c: Likewise. * opcodes/arc-dis.c (regmod_t): New type. (regmods): New structure. (fpnames): New strings with fp-regs name. (REG_PCL, REG_LIMM, REG_LIMM_S, REG_U32, REG_S32): New defines. (getregname): New function. (find_format_from_table): Discriminate between signed and unsigned 32bit immediates. (find_format): Handle extract function for flags. (arc_insn_length): Update insn lengths to various architectures. (print_insn_arc): Update printing for various ARC architectures. Signed-off-by: Claudiu Zissulescu <[email protected]> add patch 13
Removed mpymul from table. Removed extra space from ld instruction definition.
This convertion allows to pre-processor to further reduce the entries in the opcode table.
The relocation parameters with negative values lost their negative signs in an earlier commit [1]. This is an attempt to have those fixed. [1] Refactor tables for flags and operands b888972 Found-by: Claziss Zissulesco Ianculescu
The following arc64 auxiliary registers are added: 0x460 mmu_rtp0_lo 0x461 mmu_rtp0_hi 0x462 mmu_rtp1_lo 0x463 mmu_rtp1_hi 0x468 mmu_ctrl 0x469 mmu_ttbc
Signed-off-by: Claudiu Zissulescu <[email protected]>
This needs to be reworked and made safe
Fix for Github issue #531 Signed-off-by: Claudiu Zissulescu <[email protected]>
Signed-off-by: Claudiu Zissulescu <[email protected]>
Fix for Issue #523 Signed-off-by: Claudiu Zissulescu <[email protected]>
Signed-off-by: Claudiu Zissulescu <[email protected]>
Signed-off-by: Claudiu Zissulescu <[email protected]>
Fix for issue #564 The following 32 bit relocations were set as signed but should be bitfield: ARC_32_ME, ARC_GLOB_DAT, ARC_JMP_SLOT, ARC_RELATIVE Signed-off-by: Bruno Mauricio <[email protected]>
Fix for issue #565 Signed-off-by: Bruno Mauricio <[email protected]>
Based on a Tom Tromey patch 43048e4 Signed-off-by: Claudiu Zissulescu <[email protected]>
Signed-off-by: Claudiu Zissulescu <[email protected]>
As opposed to {push,pop}l_s, the {push,pop}dl_s instructions require an
even-numbered register as their operand, since only those can be used to
designate a register pair. This commit introduces a new operand type and
uses it for these two instructions.
Signed-off-by: Artemiy Volkov <[email protected]>
The R_ARC_TLS_LE_32 is defined as S + A + TLS_TBSS - TLS_REL, where
- S is the base address of the symbol in the memory
- A is the symbol addendum
- TLS_TBSS is the TLS Translation Control Block size (aligned)
- TLS_REL is the base of the TLS section
Given the next code snip:
__thread int data_var = 12;
__attribute__((__aligned__(128))) __thread int data_var_128 = 128;
__thread int bss_var;
__attribute__((__aligned__(256))) __thread int bss_var_256;
int __start(void)
{
return data_var + data_var_128 + bss_var + bss_var_256;
}
The current code returns different TLS_TBSS values for .tdata and
.tbss. This patch fixes this by using the linker provided tls_sec.
Signed-off-by: Claudiu Zissulescu <[email protected]>
Modified the regmods array to accurately reflect the changes made to the general registers in ARCv3. Signed-off-by: Luis Silva <[email protected]>
claziss
reviewed
Sep 6, 2023
Modified the name of the sign-extended long immediate, changing it from 'LIMM' to 'XLIMM' to enhance clarity and differentiation. Signed-off-by: Luis Silva <[email protected]>
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Modified the regmods array to accurately reflect the changes made to the general registers in ARCv3.
foss-for-synopsys-dwc-arc-processors/toolchain#572