more z80pio tests

floooh · Jul 18, 2024 · 4276e4c · 4276e4c
1 parent e6782c1
commit 4276e4c
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Showing 2 changed files with 46 additions and 7 deletions.
diff --git a/src/chips/z80pio.zig b/src/chips/z80pio.zig
@@ -175,18 +175,19 @@ pub fn Z80PIO(comptime P: Pins, comptime Bus: anytype) type {
             return (bus & ~DBUS) | (@as(Bus, data) << P.DBUS[0]);
         }
 
-        pub inline fn setPort(bus: Bus, comptime port: usize, data: u8) Bus {
+        pub inline fn setPort(comptime port: comptime_int, bus: Bus, data: u8) Bus {
             return switch (port) {
-                PORT.A => (bus & ~PA) | (@as(bus, data) << P.PA[0]),
-                PORT.B => (bus & ~PB) | (@as(bus, data) << P.PB[0]),
+                PORT.A => (bus & ~PA) | (@as(Bus, data) << P.PA[0]),
+                PORT.B => (bus & ~PB) | (@as(Bus, data) << P.PB[0]),
                 else => unreachable,
             };
         }
 
-        pub inline fn getPort(bus: Bus, comptime port: usize) u8 {
+        pub inline fn getPort(comptime port: comptime_int, bus: Bus) u8 {
             return @truncate(bus >> switch (port) {
                 PORT.A => P.PA[0],
                 PORT.B => P.PB[0],
+                else => unreachable,
             });
         }
 
@@ -240,7 +241,7 @@ pub fn Z80PIO(comptime P: Pins, comptime Bus: anytype) type {
             //
 
             // handle io requests
-            const p = &self.ports[if ((bus & BASEL) != 0) PORT.A else PORT.B];
+            const p = &self.ports[if ((bus & BASEL) != 0) PORT.B else PORT.A];
             switch (bus & (CE | IORQ | RD | M1 | CDSEL)) {
                 CE | IORQ | RD | CDSEL => {
                     // read control word
@@ -258,6 +259,7 @@ pub fn Z80PIO(comptime P: Pins, comptime Bus: anytype) type {
                     // write data
                     writeData(p, getData(bus));
                 },
+                else => {},
             }
             // read port bits into PIO
             self.readPorts(bus);
@@ -358,7 +360,7 @@ pub fn Z80PIO(comptime P: Pins, comptime Bus: anytype) type {
             inline for (&self.ports, 0..) |*p, pid| {
                 const data = switch (p.mode) {
                     MODE.OUTPUT => p.output,
-                    MODE.INPIUT, MODE.BIDIRECTIONAL => 0xFF,
+                    MODE.INPUT, MODE.BIDIRECTIONAL => 0xFF,
                     MODE.BITCONTROL => p.io_select | (p.output & ~p.io_select),
                 };
                 bus = setPort(pid, bus, data);
@@ -397,6 +399,7 @@ pub fn Z80PIO(comptime P: Pins, comptime Bus: anytype) type {
                             }
                             p.bctrl_match = match;
                         },
+                        else => {},
                     }
                 }
             }

diff --git a/tests/z80pio.test.zig b/tests/z80pio.test.zig
@@ -6,6 +6,15 @@ const z80pio = chipz.chips.z80pio;
 const Bus = u64;
 const Z80PIO = z80pio.Z80PIO(z80pio.DefaultPins, Bus);
 
+const setData = Z80PIO.setData;
+
+const IORQ = Z80PIO.IORQ;
+const RD = Z80PIO.RD;
+const CE = Z80PIO.CE;
+const BASEL = Z80PIO.BASEL;
+const CDSEL = Z80PIO.CDSEL;
+
+const PORT = Z80PIO.PORT;
 const MODE = Z80PIO.MODE;
 const INTCTRL = Z80PIO.INTCTRL;
 
@@ -18,4 +27,31 @@ test "init Z80PIO" {
     }
 }
 
-// FIXME: more tests
+test "write interrupt vector" {
+    var pio = Z80PIO.init();
+
+    // port A...
+    _ = pio.tick(setData(CE | IORQ | CDSEL, 0xEE));
+    try expect(!pio.reset_active);
+    try expect(pio.ports[PORT.A].irq.vector == 0xEE);
+    try expect(0 != (pio.ports[PORT.A].int_control & INTCTRL.EI));
+    try expect(pio.ports[PORT.A].int_enabled);
+
+    // port B...
+    _ = pio.tick(setData(CE | IORQ | BASEL | CDSEL, 0xCC));
+    try expect(pio.ports[PORT.B].irq.vector == 0xCC);
+    try expect(0 != (pio.ports[PORT.B].int_control & INTCTRL.EI));
+    try expect(pio.ports[PORT.B].int_enabled);
+}
+
+test "set input/output mode" {
+    var pio = Z80PIO.init();
+
+    // set port A to output...
+    _ = pio.tick(setData(CE | IORQ | CDSEL, (@as(u8, MODE.OUTPUT) << 6) | 0x0F));
+    try expect(pio.ports[PORT.A].mode == MODE.OUTPUT);
+
+    // set port B to input...
+    _ = pio.tick(setData(CE | IORQ | BASEL | CDSEL, (@as(u8, MODE.INPUT) << 6) | 0x0F));
+    try expect(pio.ports[PORT.B].mode == MODE.INPUT);
+}