[WIP] Rebar refactoring

.gitmodules

@@ -16,3 +16,9 @@
 [submodule "boom"]
 	path = boom
 	url = https://github.com/ucb-bar/riscv-boom.git
+[submodule "firesim"]
+	path = firesim
+	url = https://github.com/firesim/firesim.git
+[submodule "tools/firrtl"]
+	path = tools/firrtl
+	url = https://github.com/freechipsproject/firrtl.git

Makefrag

@@ -1,20 +1,26 @@
 ROCKETCHIP_DIR=$(base_dir)/rocket-chip
 
-SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++2.12.4
+SBT ?= java -Xmx16G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++2.12.4
 
 lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
 
-PACKAGES=rocket-chip testchipip icenet sifive-blocks
+PACKAGES=testchipip icenet sifive-blocks \
+	$(addprefix firesim/sim/, . midas midas/targetutils) \
+	$(addprefix $(ROCKETCHIP_DIR)/, . hardfloat)
+
 SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
-ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-2.12/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-2.12/*"
+# NB: The rocketchip hack below
+ROCKET_CLASSES ?= $(ROCKETCHIP_DIR)/src/target/scala-2.12/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-2.12/*
 
-FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
+FIRRTL_DIR  ?= $(base_dir)/tools/firrtl
+FIRRTL_JAR ?= $(base_dir)/lib/firrtl.jar
+# TODO: FIXME
 FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR) firrtl.Driver
 
-$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
-	$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
-	mkdir -p $(ROCKETCHIP_DIR)/lib
-	cp $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $(FIRRTL_JAR)
+$(FIRRTL_JAR): $(call lookup_scala_srcs, $(FIRRTL_DIR)/src/main/scala)
+	$(MAKE) -C $(FIRRTL_DIR) SBT="$(SBT)" root_dir=$(FIRRTL_DIR) build-scala
+	mkdir -p $(@D)
+	cp $(FIRRTL_DIR)/utils/bin/firrtl.jar $(FIRRTL_JAR)
 
 build_dir=$(sim_dir)/generated-src
 testchip_dir = $(base_dir)/testchipip

build.sbt

@@ -6,14 +6,53 @@ lazy val commonSettings = Seq(
   scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
   libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.1" % "test",
   libraryDependencies += "org.json4s" %% "json4s-native" % "3.5.3",
+  libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.5.3",
   libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
   addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
     Resolver.sonatypeRepo("releases"),
     Resolver.mavenLocal))
 
-lazy val rocketchip = RootProject(file("rocket-chip"))
+val rocketChipDir = file("rocket-chip")
+
+lazy val firesimAsLibrary = sys.env.get("FIRESIM_IS_TOP") == None
+lazy val firesimDir = if (firesimAsLibrary) {
+  file("firesim/sim/")
+} else {
+  file("../../sim/")
+}
+
+// Subproject definitions begin
+// NB: FIRRTL dependency is unmanaged (and dropped in sim/lib)
+lazy val chisel  = (project in rocketChipDir / "chisel3")
+
+// Contains annotations & firrtl passes you may wish to use in rocket-chip without
+// introducing a circular dependency between RC and MIDAS
+lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
+
+// Rocket-chip dependencies (subsumes making RC a RootProject)
+lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
+  .settings(
+    commonSettings,
+    crossScalaVersions := Seq("2.11.12", "2.12.4"))
+  .dependsOn(chisel, midasTargetUtils)
+
+
+lazy val macros     = (project in rocketChipDir / "macros")
+  .settings(commonSettings,
+  )
+
+// HACK: I'm strugging to override settings in rocket-chip's build.sbt (i want
+// the subproject to register a new library dependendency on midas's targetutils library)
+// So instead, avoid the existing build.sbt altogether and specify the project's root at src/
+
+lazy val rocketchip = (project in rocketChipDir / "src")
+             .settings(
+               commonSettings,
+               scalaSource in Compile := baseDirectory.value / "main" / "scala",
+               resourceDirectory in Compile := baseDirectory.value / "main" / "resources")
+             .dependsOn(chisel, hardfloat, macros)
 
 lazy val sifive_blocks = (project in file("sifive-blocks")).settings(commonSettings).dependsOn(rocketchip)
 
@@ -23,4 +62,11 @@ lazy val icenet = project.settings(commonSettings).dependsOn(rocketchip, testchi
 
 lazy val boom = project.settings(commonSettings).dependsOn(rocketchip)
 
-lazy val example = (project in file(".")).settings(commonSettings).dependsOn(boom, icenet, testchipip, sifive_blocks)
+// The library components of FireSim
+lazy val midas   = ProjectRef(firesimDir, "midas")
+lazy val firesim = ProjectRef(firesimDir, "common")
+
+lazy val firechip = (project in file("."))
+    .settings(commonSettings)
+    .dependsOn(boom, icenet, testchipip, sifive_blocks, midasTargetUtils, midas,
+      firesim % "test->test;compile->compile")

project/build.properties

@@ -0,0 +1 @@
+sbt.version=1.1.1

project/plugins.sbt

@@ -0,0 +1,19 @@
+resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
+
+resolvers += "simplytyped" at "http://simplytyped.github.io/repo/releases"
+
+addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2")
+
+addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1")
+
+addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6")
+
+addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1")
+
+addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
+
+addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1")
+
+addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3")
+
+addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")

src/main/scala/firesim/Generator.scala

@@ -0,0 +1,122 @@
+package firesim.firesim
+
+import java.io.{File}
+
+import chisel3.experimental.RawModule
+import chisel3.internal.firrtl.{Circuit, Port}
+
+import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
+import freechips.rocketchip.devices.debug.DebugIO
+import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts}
+import freechips.rocketchip.system.DefaultTestSuites._
+import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.subsystem.RocketTilesKey
+import freechips.rocketchip.tile.XLen
+
+import boom.system.{BoomTilesKey, BoomTestSuites}
+
+import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities}
+
+trait HasTestSuites {
+  val rv64RegrTestNames = collection.mutable.LinkedHashSet(
+      "rv64ud-v-fcvt",
+      "rv64ud-p-fdiv",
+      "rv64ud-v-fadd",
+      "rv64uf-v-fadd",
+      "rv64um-v-mul",
+      // "rv64mi-p-breakpoint", // Not implemented in BOOM
+      // "rv64uc-v-rvc", // Not implemented in BOOM
+      "rv64ud-v-structural",
+      "rv64si-p-wfi",
+      "rv64um-v-divw",
+      "rv64ua-v-lrsc",
+      "rv64ui-v-fence_i",
+      "rv64ud-v-fcvt_w",
+      "rv64uf-v-fmin",
+      "rv64ui-v-sb",
+      "rv64ua-v-amomax_d",
+      "rv64ud-v-move",
+      "rv64ud-v-fclass",
+      "rv64ua-v-amoand_d",
+      "rv64ua-v-amoxor_d",
+      "rv64si-p-sbreak",
+      "rv64ud-v-fmadd",
+      "rv64uf-v-ldst",
+      "rv64um-v-mulh",
+      "rv64si-p-dirty")
+
+  val rv32RegrTestNames = collection.mutable.LinkedHashSet(
+      "rv32mi-p-ma_addr",
+      "rv32mi-p-csr",
+      "rv32ui-p-sh",
+      "rv32ui-p-lh",
+      "rv32uc-p-rvc",
+      "rv32mi-p-sbreak",
+      "rv32ui-p-sll")
+
+  def addTestSuites(targetName: String, params: Parameters) {
+    val coreParams =
+      if (params(RocketTilesKey).nonEmpty) {
+        params(RocketTilesKey).head.core
+      } else {
+        params(BoomTilesKey).head.core
+      }
+    val xlen = params(XLen)
+    val vm = coreParams.useVM
+    val env = if (vm) List("p","v") else List("p")
+    coreParams.fpu foreach { case cfg =>
+      if (xlen == 32) {
+        TestGeneration.addSuites(env.map(rv32uf))
+        if (cfg.fLen >= 64)
+          TestGeneration.addSuites(env.map(rv32ud))
+      } else {
+        TestGeneration.addSuite(rv32udBenchmarks)
+        TestGeneration.addSuites(env.map(rv64uf))
+        if (cfg.fLen >= 64)
+          TestGeneration.addSuites(env.map(rv64ud))
+      }
+    }
+    if (coreParams.useAtomics)    TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+    if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+    val (rvi, rvu) =
+      if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
+      else if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+      else            ((if (vm) rv32i else rv32pi), rv32u)
+
+    TestGeneration.addSuites(rvi.map(_("p")))
+    TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+    TestGeneration.addSuite(benchmarks)
+    TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    TestGeneration.addSuite(FastBlockdevTests)
+    TestGeneration.addSuite(SlowBlockdevTests)
+    if (!targetName.contains("NoNIC"))
+      TestGeneration.addSuite(NICLoopbackTests)
+  }
+}
+
+// Mixed into an App or into a TestSuite
+trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites {
+  /** Output software test Makefrags, which provide targets for integration testing. */
+  def generateTestSuiteMakefrags {
+    addTestSuites(names.topModuleClass, targetParams)
+    writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites
+  }
+
+  // Output miscellaneous files produced as a side-effect of elaboration
+  def generateArtefacts {
+    ElaborationArtefacts.files.foreach { case (extension, contents) =>
+      writeOutputFile(s"${longName}.${extension}", contents ())
+    }
+  }
+}
+
+object FireSimGenerator extends App with IsFireSimGeneratorLike {
+  lazy val generatorArgs = GeneratorArgs(args)
+  lazy val genDir = new File(names.targetDir)
+
+  elaborateAndCompileWithMidas
+  generateTestSuiteMakefrags
+  generateHostVerilogHeader
+  generateArtefacts
+}

src/main/scala/firesim/SimConfigs.scala

@@ -0,0 +1,131 @@
+package firesim.firesim
+
+import freechips.rocketchip.config.{Parameters, Config, Field}
+
+import midas.{EndpointKey}
+import midas.widgets.{EndpointMap}
+import midas.models._
+
+import testchipip.{WithBlockDevice}
+
+import firesim.endpoints._
+import firesim.configs._
+
+class WithSerialWidget extends Config((site, here, up) => {
+  case EndpointKey => up(EndpointKey) ++ EndpointMap(Seq(new SimSerialIO))
+})
+
+class WithUARTWidget extends Config((site, here, up) => {
+  case EndpointKey => up(EndpointKey) ++ EndpointMap(Seq(new SimUART))
+})
+
+class WithSimpleNICWidget extends Config((site, here, up) => {
+  case EndpointKey => up(EndpointKey) ++ EndpointMap(Seq(new SimSimpleNIC))
+  case LoopbackNIC => false
+})
+
+class WithBlockDevWidget extends Config((site, here, up) => {
+  case EndpointKey => up(EndpointKey) ++ EndpointMap(Seq(new SimBlockDev))
+})
+
+class WithTracerVWidget extends Config((site, here, up) => {
+  case midas.EndpointKey => up(midas.EndpointKey) ++
+    EndpointMap(Seq(new SimTracerV))
+})
+
+/*******************************************************************************
+* Full PLATFORM_CONFIG Configurations. These set simulator parameters.
+*
+* In general, if you're adding or removing features from any of these, you
+* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
+* will store this name as part of the tags for the AGFI, so that later you can
+* reconstruct what is in a particular AGFI. These tags are also used to
+* determine which driver to build.
+*******************************************************************************/
+class FireSimConfig extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new WithSerialWidget ++
+  new WithUARTWidget ++
+  new WithSimpleNICWidget ++
+  new WithBlockDevWidget ++
+  new WithDefaultMemModel ++
+  new WithTracerVWidget ++
+  new BasePlatformConfig)
+
+class FireSimConfig160MHz extends Config(
+  new WithDesiredHostFrequency(160) ++
+  new FireSimConfig)
+
+class FireSimConfig90MHz extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new FireSimConfig)
+
+class FireSimConfig75MHz extends Config(
+  new WithDesiredHostFrequency(75) ++
+  new FireSimConfig)
+
+class FireSimClockDivConfig extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new WithSerialWidget ++
+  new WithUARTWidget ++
+  new WithSimpleNICWidget ++
+  new WithBlockDevWidget ++
+  new WithDefaultMemModel(clockDivision = 2) ++
+  new BasePlatformConfig)
+
+class FireSimDDR3Config extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new WithSerialWidget ++
+  new WithUARTWidget ++
+  new WithSimpleNICWidget ++
+  new WithBlockDevWidget ++
+  new FCFS16GBQuadRank ++
+  new BasePlatformConfig)
+
+class FireSimDDR3LLC4MBConfig extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new WithSerialWidget ++
+  new WithUARTWidget ++
+  new WithSimpleNICWidget ++
+  new WithBlockDevWidget ++
+  new FCFS16GBQuadRankLLC4MB ++
+  new BasePlatformConfig)
+
+class FireSimDDR3FRFCFSConfig extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new WithSerialWidget ++
+  new WithUARTWidget ++
+  new WithSimpleNICWidget ++
+  new WithBlockDevWidget ++
+  new FRFCFS16GBQuadRank ++
+  new BasePlatformConfig)
+
+class FireSimDDR3FRFCFSLLC4MBConfig extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new WithSerialWidget ++
+  new WithUARTWidget ++
+  new WithSimpleNICWidget ++
+  new WithBlockDevWidget ++
+  new FRFCFS16GBQuadRankLLC4MB ++
+  new BasePlatformConfig)
+
+class FireSimDDR3FRFCFSLLC4MBConfig160MHz extends Config(
+  new WithDesiredHostFrequency(160) ++
+  new FireSimDDR3FRFCFSLLC4MBConfig)
+
+class FireSimDDR3FRFCFSLLC4MBConfig90MHz extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new FireSimDDR3FRFCFSLLC4MBConfig)
+
+class FireSimDDR3FRFCFSLLC4MBConfig75MHz extends Config(
+  new WithDesiredHostFrequency(75) ++
+  new FireSimDDR3FRFCFSLLC4MBConfig)
+
+class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config(
+  new WithDesiredHostFrequency(90) ++
+  new WithSerialWidget ++
+  new WithUARTWidget ++
+  new WithSimpleNICWidget ++
+  new WithBlockDevWidget ++
+  new FRFCFS16GBQuadRankLLC4MB3Div ++
+  new BasePlatformConfig)