changes for new rocket-chip

firesim · Jan 16, 2018 · ed13397 · ed13397
1 parent 269660b
commit ed13397
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Showing 5 changed files with 17 additions and 4 deletions.
diff --git a/rocket-chip b/rocket-chip
diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
@@ -3,8 +3,8 @@ package example
 import chisel3._
 import freechips.rocketchip.config.{Parameters, Config}
 import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
+import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.devices.tilelink.BootROMParams
-import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.tile.XLen
 import testchipip._
 
@@ -13,9 +13,15 @@ class WithBootROM extends Config((site, here, up) => {
     contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
 })
 
+object ConfigValName {
+  implicit val valName = ValName("TestHarness")
+}
+import ConfigValName._
+
 class WithExampleTop extends Config((site, here, up) => {
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
     Module(LazyModule(new ExampleTop()(p)).module)
+  }
 })
 
 class WithPWM extends Config((site, here, up) => {

diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
@@ -13,7 +13,10 @@ class TestHarness(implicit val p: Parameters) extends Module {
   })
 
   val dut = p(BuildTop)(clock, reset.toBool, p)
+  dut.debug := DontCare
   dut.connectSimAXIMem()
+  dut.dontTouchPorts()
+  dut.tieOffInterrupts()
   io.success := dut.connectSimSerial()
 }
 

diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala
@@ -4,12 +4,14 @@ import chisel3._
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.util.DontTouch
 import testchipip._
 
 class ExampleTop(implicit p: Parameters) extends RocketCoreplex
     with HasMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasSystemErrorSlave
+    with HasSyncExtInterrupts
     with HasNoDebug
     with HasPeripherySerial {
   override lazy val module = new ExampleTopModule(this)
@@ -19,8 +21,10 @@ class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketCoreplexModule(l)
     with HasRTCModuleImp
     with HasMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
+    with HasExtInterruptsModuleImp
     with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
+    with DontTouch
 
 class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop
     with HasPeripheryPWM {

diff --git a/testchipip b/testchipip
+4 −3		src/main/scala/BlockDevice.scala
+2 −2		src/main/scala/Unittests.scala
+31 −0		src/main/scala/Util.scala