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* Release candidate for V1.4.4 Fixes Simulations when using 3rd party simulators * updating sh_ddr interface to shell V1.4 in cl_template file.
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Hardware Debug of SDAccel OpenCL Kernel | ||
====================== | ||
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This file contains the following sections: | ||
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1. Overview | ||
2. Enabling ChipScope Debug | ||
3. Host code changes to support debugging | ||
4. Building the executable, creating the AFI, and executing the host code | ||
5. Start debug servers | ||
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## 1. Overview | ||
The sections below give you a brief explanation of the steps required to debug your SDAccel OpenCL kernel. They include enabling ChipScope debug, pausing the execution of the host code at the appropriate stage to ensure the setup of ILA triggers, building the running the host code and starting the debug servers to debug the design in hardware. | ||
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## 2. Enabling ChipScope Debug | ||
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Debug cores can be added to the AXI interfaces on the kernel itself to monitor AXI transaction level activity (part of the ChipScope Debug feature of SDAccel). | ||
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Adding debug cores to the AXI interfaces on the kernel can be done in a couple of ways: | ||
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- Using the SDAccel GUI and enabling "ChipScope Debug" on the hardware function in the Hardware Function Settings window. | ||
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- Note: If you are building on AWS and need information on how to enable the SDAccel GUI on AWS F1, see [README_GUI.md](./README_GUI.md). If you are building on premise, follow the directions in [On_Premises_Development_Steps.md](./On_Premises_Development_Steps.md). | ||
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- Using the XOCC --dk chipscope option with the compute unit name and optional interface name. | ||
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To enable ChipScope debug using the GUI, perform the following steps: | ||
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1. In the assistant window, under System build configuration, right-click on the compute unit that you want to enable ChipScope debug on and click settings. | ||
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 | ||
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2. When the hardware function settings dialog appears, check the box for "ChipScope Debug" in the debug and profiling settings table. By checking this box, the compute unit will now have a System ILA inserted onto it's AXI interface ports. | ||
 | ||
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Alternatively, ChipScope debug can be enabled by adding an XOCC option to the CLFLAGS in the makefile. This method allows the ChipScope debug feature to be enabled without invoking the SDAccel GUI. The --dk option shown below shows the general usage: | ||
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``` | ||
--dk chipscope:<compute_unit_name>:<interface_name> | ||
``` | ||
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For example, to add ChipScope debugging to the helloworld_ocl OpenCL example , enabling chipscope debug can be accomplished by adding the following XOCC option to the CLFLAGS in the makefile: | ||
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``` | ||
--dk chipscope:krnl_vadd_1 | ||
``` | ||
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For detailed usage and more examples, refer to the SDAccel Debugging Guide (UG1281 v2018.2). | ||
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## 3. Host code changes to support debugging | ||
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The application host code needs to be modified to ensure you can set up the ILA trigger conditions **prior** to running the kernel. | ||
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The host code shown below introduces the wait for the setup of ILA Trigger conditions and the arming of the ILA. | ||
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src/host.cpp | ||
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void wait_for_enter(const std::string& msg) | ||
{ | ||
std::cout << msg << std::endl; | ||
std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n'); | ||
} | ||
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... | ||
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cl::Program::Binaries bins = xcl::import_binary_file(binaryFile); | ||
devices.resize(1); | ||
cl::Program program(context, devices, bins); | ||
cl::Kernel krnl_vadd(program,"krnl_vadd_rtl"); | ||
wait_for_enter("\nPress ENTER to continue after setting up ILA trigger..."); | ||
//Allocate Buffer in Global Memory | ||
... | ||
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//Launch the Kernel | ||
q.enqueueTask(krnl_vadd); | ||
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## 4. Building the executable, creating the AFI and executing the host code | ||
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- **Build the executable** in your design directory (`your_design_directory`) by running the steps below: | ||
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``` | ||
cd your_design_directory | ||
make all DEVICES=$AWS_PLATFORM | ||
``` | ||
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- **Creating and registering the AFI** | ||
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Please note, the angle bracket directories need to be replaced according to the user setup. | ||
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``` | ||
$SDACCEL_DIR/tools/create_sdaccel_afi.sh -xclbin=your_design.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin -o=your_design.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin -s3_bucket=<bucket-s3_dcp_key=<f1-dcp-folder-s3_logs_key=<f1-logs> | ||
``` | ||
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- **Setup and Execute** | ||
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``` | ||
$ sudo sh | ||
# source /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh | ||
# ./host | ||
``` | ||
This produces the following output: | ||
``` | ||
Device/Slot[0] (/dev/xdma0, 0:0:1d.0) | ||
xclProbe found 1 FPGA slots with XDMA driver running | ||
platform Name: Xilinx | ||
Vendor Name : Xilinx | ||
Found Platform | ||
XCLBIN File Name: vadd | ||
INFO: Importing ./binary_container_1.awsxclbin | ||
Loading: './binary_container_1.awsxclbin' | ||
Successfully skipped reloading of local image. | ||
Press ENTER to continue after setting up ILA trigger... | ||
``` | ||
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## 5. Start Debug Servers | ||
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#### Starting Debug Servers on Amazon F1 instance | ||
Instructions to start the debug servers on an Amazon F1 instance can be found [here](../../hdk/docs/Virtual_JTAG_XVC.md). | ||
Once you have setup your ILA triggers and armed the ILA core, you can now Press Enter on your host to continue execution of the application and RTL Kernel. | ||
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