run make format and added docstrings

Signed-off-by: Alessandro Comodi <[email protected]>

xc/xc7/tests/soc/litex/fixup_xdc.py

@@ -1,7 +1,25 @@
 import argparse
+"""
+Currently, litex outputs XDC constraints in which the create_clock commands
+cannot be correctly parsed yet by the XDC yosys plugin.
+
+Example of failing XDC command:
+    create_clock -name clk100 -period 10.0 [get_nets clk100]
+
+Example of working XDC command:
+    create_clock -period 10.0 clk100
+
+This script fixes the generated XDC and translates the failing commands
+into the working ones.
+
+This script is a temporary workaround and needs to be avoided.
+"""
+
 
 def main():
-    parser = argparse.ArgumentParser(description="Fixup script to modify the XDC output of LiteX")
+    parser = argparse.ArgumentParser(
+        description="Fixup script to modify the XDC output of LiteX"
+    )
     parser.add_argument("--xdc", required=True)
 
     args = parser.parse_args()
@@ -21,7 +39,9 @@ def main():
 
                     # Old line: create_clock -name clk100 -period 10.0 [get_nets clk100]
                     # New line: create_clock -period 10.0 clk100
-                    new_line = " ".join([groups[0], groups[3], groups[4], groups[2], '\n'])
+                    new_line = " ".join(
+                        [groups[0], groups[3], groups[4], groups[2], '\n']
+                    )
 
                     lines_to_add.append(new_line)
             else:
@@ -31,5 +51,6 @@ def main():
         for line in lines_to_add:
             xdc.write(line)
 
+
 if __name__ == "__main__":
     main()

xc/xc7/tests/soc/litex/generate.py

@@ -16,55 +16,82 @@
 from litedram.modules import MT41K128M16
 from litedram.phy import s7ddrphy
 
+
 class BaseSoC(SoCCore):
-    def __init__(self, toolchain="vivado", sys_clk_freq=int(60e6),
-                 with_ethernet=False, with_ram=False, board_variant="a7-35", **kwargs):
+    def __init__(
+            self,
+            toolchain="vivado",
+            sys_clk_freq=int(60e6),
+            with_ethernet=False,
+            with_ram=False,
+            board_variant="a7-35",
+            **kwargs
+    ):
 
         platform = arty.Platform(variant=board_variant, toolchain=toolchain)
-        SoCCore.__init__(self, platform, sys_clk_freq,
-            ident          = "LiteX SoC on Arty A7",
-            ident_version  = True,
-            **kwargs)
+        SoCCore.__init__(
+            self,
+            platform,
+            sys_clk_freq,
+            ident="LiteX SoC on Arty A7",
+            ident_version=True,
+            **kwargs
+        )
 
         self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain)
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if with_ram:
-            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
-                memtype        = "DDR3",
-                nphases        = 4,
-                sys_clk_freq   = sys_clk_freq)
+            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
+                platform.request("ddram"),
+                memtype="DDR3",
+                nphases=4,
+                sys_clk_freq=sys_clk_freq
+            )
             self.add_csr("ddrphy")
-            self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K128M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+            self.add_sdram(
+                "sdram",
+                phy=self.ddrphy,
+                module=MT41K128M16(sys_clk_freq, "1:4"),
+                origin=self.mem_map["main_ram"],
+                size=kwargs.get("max_sdram_size", 0x40000000),
+                l2_cache_size=kwargs.get("l2_size", 8192),
+                l2_cache_min_data_width=kwargs.get("min_l2_data_width", 128),
+                l2_cache_reverse=True
             )
 
         if with_ethernet:
             self.submodules.ethphy = LiteEthPHYMII(
-                clock_pads = self.platform.request("eth_clocks"),
-                pads       = self.platform.request("eth"))
+                clock_pads=self.platform.request("eth_clocks"),
+                pads=self.platform.request("eth")
+            )
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
         self.submodules.leds = LedChaser(
-            pads         = platform.request_all("user_led"),
-            sys_clk_freq = sys_clk_freq)
+            pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq
+        )
         self.add_csr("leds")
 
+
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--load", action="store_true", help="Load bitstream")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--toolchain", default="vivado", help="Gateware toolchain to use, vivado or symbiflow (default)")
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
-    parser.add_argument("--with-ram",  action="store_true", help="Enable Main RAM")
-    parser.add_argument("--board", default="a7-35", help="Specifies Arty Board version")
+    parser.add_argument(
+        "--toolchain",
+        default="vivado",
+        help="Gateware toolchain to use, vivado or symbiflow (default)"
+    )
+    parser.add_argument(
+        "--with-ethernet", action="store_true", help="Enable Ethernet support"
+    )
+    parser.add_argument(
+        "--with-ram", action="store_true", help="Enable Main RAM"
+    )
+    parser.add_argument(
+        "--board", default="a7-35", help="Specifies Arty Board version"
+    )
     parser.add_argument("--builddir", help="Build directory")
 
     soc_core_args(parser)
@@ -84,12 +111,16 @@ def main():
     )
 
     builder = Builder(soc, output_dir=args.builddir)
-    builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
+    builder_kwargs = vivado_build_argdict(
+        args
+    ) if args.toolchain == "vivado" else {}
     builder.build(**builder_kwargs, run=args.build)
 
     if args.load:
         prog = soc.platform.create_programmer()
-        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+        prog.load_bitstream(
+            os.path.join(builder.gateware_dir, soc.build_name + ".bit")
+        )
 
 
 if __name__ == "__main__":