Various fixes and updates

Cargo.toml

@@ -21,12 +21,11 @@ exclude = [
 edition = "2018"
 
 [dependencies]
-cortex-m = "0.6.2"
+cortex-m = "0.7"
 embedded-dma = "0.1"
 nb = "0.1.1"
 stm32wb-pac = "0.2"
 as-slice = "0.1"
-cortex-m-semihosting = { version = "0.3.5", features = ["jlink-quirks"] }
 bit_field = "0.10.0"
 heapless = "0.5.3"
 
@@ -82,3 +81,6 @@ codegen-units = 1
 codegen-units = 1
 debug = true
 lto = true
+
+[package.metadata.docs.rs]
+features = ["xG-package", "stm32-usbd"]

src/gpio.rs

@@ -95,12 +95,11 @@ pub struct AF14;
 /// Alternate function 15 (type state)
 pub struct AF15;
 
-#[allow(non_camel_case_types)]
 #[derive(Debug, PartialEq)]
 pub enum Edge {
-    RISING,
-    FALLING,
-    RISING_FALLING,
+    Rising,
+    Falling,
+    RisingFalling,
 }
 
 /// External Interrupt Pin
@@ -318,15 +317,15 @@ macro_rules! gpio {
                 /// Generate interrupt on rising edge, falling edge or both
                 fn trigger_on_edge(&mut self, exti: &mut EXTI, edge: Edge) {
                     match edge {
-                        Edge::RISING => {
+                        Edge::Rising => {
                             exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.i)) });
                             exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.i)) });
                         },
-                        Edge::FALLING => {
+                        Edge::Falling => {
                             exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.i)) });
                             exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.i)) });
                         },
-                        Edge::RISING_FALLING => {
+                        Edge::RisingFalling => {
                             exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.i)) });
                             exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.i)) });
                         }
@@ -583,15 +582,15 @@ macro_rules! gpio {
                     /// Generate interrupt on rising edge, falling edge or both
                     fn trigger_on_edge(&mut self, exti: &mut EXTI, edge: Edge) {
                         match edge {
-                            Edge::RISING => {
+                            Edge::Rising => {
                                 exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << $i)) });
                                 exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << $i)) });
                             },
-                            Edge::FALLING => {
+                            Edge::Falling => {
                                 exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << $i)) });
                                 exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << $i)) });
                             },
-                            Edge::RISING_FALLING => {
+                            Edge::RisingFalling => {
                                 exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << $i)) });
                                 exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << $i)) });
                             }

src/prelude.rs

@@ -7,7 +7,7 @@ pub use embedded_hal::digital::v2::OutputPin;
 pub use crate::datetime::U32Ext as _stm32wb_hal_datetime_U32Ext;
 pub use crate::ipcc::IpccExt as _stm32wb_hal_ipcc_IpccExt;
 //pub use crate::dma::DmaExt as _stm32wb_hal_DmaExt;
-//pub use crate::flash::FlashExt as _stm32wb_hal_FlashExt;
+pub use crate::flash::FlashExt as _stm32wb_hal_FlashExt;
 pub use crate::gpio::GpioExt as _stm32wb_hal_GpioExt;
 pub use crate::pwm::PwmExt1 as _stm32l4_hal_PwmExt1;
 pub use crate::pwm::PwmExt2 as _stm32l4_hal_PwmExt2;

src/rcc/mod.rs

@@ -51,12 +51,17 @@ impl Rcc {
             SysClkSrc::Msi(_msi_range) => todo!(),
             SysClkSrc::Hsi => todo!(),
             SysClkSrc::HseSys(hse_div) => {
-                self.clocks.hse = Some(HSE_FREQ.hz());
-
-                self.clocks.sysclk = match hse_div {
-                    HseDivider::NotDivided => HSE_FREQ.hz(),
-                    HseDivider::Div2 => (HSE_FREQ / 2).hz(),
+                // Actually turn on and use HSE....
+                let (divided, f_input) = match hse_div {
+                    HseDivider::NotDivided => (false, HSE_FREQ),
+                    HseDivider::Div2 => (true, HSE_FREQ / 2),
                 };
+                self.rb.cr.modify(|_, w| w.hsepre().bit(divided).hseon().set_bit());
+                // Wait for HSE startup
+                while !self.rb.cr.read().hserdy().bit_is_set() {}
+
+                self.clocks.hse = Some(HSE_FREQ.hz());
+                self.clocks.sysclk = f_input.hz();
 
                 0b10
             }
@@ -83,7 +88,7 @@ impl Rcc {
             })
         });
 
-        // Configure SYSCLK mux to use PLL clock
+        // Configure SYSCLK mux to use selected clock
         self.rb
             .cfgr
             .modify(|_r, w| unsafe { w.sw().bits(sysclk_bits) });