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changed to no longer use esp-idf-cxx SPI subsystem for LCD because it…
… abuses memory. updated with working controller input (new controller component using new espp::Joystick component)
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boxart/004 Pokemon-Crystal Version-image.jpg
100755 → 100644
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3 changes: 1 addition & 2 deletions
3
boxart/resize.bash → boxart/source/resize.bash
100644 → 100755
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#!/bin/bash | ||
mkdir -p _100x100 | ||
find . -maxdepth 1 -iname "*.jpg" | xargs -L1 -I{} convert -resize 100x100 "{}" _100x100/"{}" | ||
find . -maxdepth 1 -iname "*.jpg" | xargs -L1 -I{} convert -resize 100x100 "{}" ../"{}" |
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idf_component_register( | ||
INCLUDE_DIRS "include" | ||
SRC_DIRS "src" | ||
REQUIRES "driver" "esp_lcd" "spi_flash" "nvs_flash" "codec" "esp-idf-cxx" "display" "display_drivers" | ||
REQUIRES "driver" "esp_lcd" "spi_flash" "nvs_flash" "codec" "display" "display_drivers" "controller" | ||
) |
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#pragma once | ||
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/*========================================================================= | ||
I2C ADDRESS/BITS | ||
-----------------------------------------------------------------------*/ | ||
#define ADS1X15_ADDRESS (0x48) ///< 1001 000 (ADDR = GND) | ||
/*=========================================================================*/ | ||
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/*========================================================================= | ||
POINTER REGISTER | ||
-----------------------------------------------------------------------*/ | ||
#define ADS1X15_REG_POINTER_MASK (0x03) ///< Point mask | ||
#define ADS1X15_REG_POINTER_CONVERT (0x00) ///< Conversion | ||
#define ADS1X15_REG_POINTER_CONFIG (0x01) ///< Configuration | ||
#define ADS1X15_REG_POINTER_LOWTHRESH (0x02) ///< Low threshold | ||
#define ADS1X15_REG_POINTER_HITHRESH (0x03) ///< High threshold | ||
/*=========================================================================*/ | ||
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/*========================================================================= | ||
CONFIG REGISTER | ||
-----------------------------------------------------------------------*/ | ||
#define ADS1X15_REG_CONFIG_OS_MASK (0x8000) ///< OS Mask | ||
#define ADS1X15_REG_CONFIG_OS_SINGLE \ | ||
(0x8000) ///< Write: Set to start a single-conversion | ||
#define ADS1X15_REG_CONFIG_OS_BUSY \ | ||
(0x0000) ///< Read: Bit = 0 when conversion is in progress | ||
#define ADS1X15_REG_CONFIG_OS_NOTBUSY \ | ||
(0x8000) ///< Read: Bit = 1 when device is not performing a conversion | ||
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#define ADS1X15_REG_CONFIG_MUX_MASK (0x7000) ///< Mux Mask | ||
#define ADS1X15_REG_CONFIG_MUX_DIFF_0_1 \ | ||
(0x0000) ///< Differential P = AIN0, N = AIN1 (default) | ||
#define ADS1X15_REG_CONFIG_MUX_DIFF_0_3 \ | ||
(0x1000) ///< Differential P = AIN0, N = AIN3 | ||
#define ADS1X15_REG_CONFIG_MUX_DIFF_1_3 \ | ||
(0x2000) ///< Differential P = AIN1, N = AIN3 | ||
#define ADS1X15_REG_CONFIG_MUX_DIFF_2_3 \ | ||
(0x3000) ///< Differential P = AIN2, N = AIN3 | ||
#define ADS1X15_REG_CONFIG_MUX_SINGLE_0 (0x4000) ///< Single-ended AIN0 | ||
#define ADS1X15_REG_CONFIG_MUX_SINGLE_1 (0x5000) ///< Single-ended AIN1 | ||
#define ADS1X15_REG_CONFIG_MUX_SINGLE_2 (0x6000) ///< Single-ended AIN2 | ||
#define ADS1X15_REG_CONFIG_MUX_SINGLE_3 (0x7000) ///< Single-ended AIN3 | ||
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constexpr uint16_t MUX_BY_CHANNEL[] = { | ||
ADS1X15_REG_CONFIG_MUX_SINGLE_0, ///< Single-ended AIN0 | ||
ADS1X15_REG_CONFIG_MUX_SINGLE_1, ///< Single-ended AIN1 | ||
ADS1X15_REG_CONFIG_MUX_SINGLE_2, ///< Single-ended AIN2 | ||
ADS1X15_REG_CONFIG_MUX_SINGLE_3 ///< Single-ended AIN3 | ||
}; ///< MUX config by channel | ||
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#define ADS1X15_REG_CONFIG_PGA_MASK (0x0E00) ///< PGA Mask | ||
#define ADS1X15_REG_CONFIG_PGA_6_144V (0x0000) ///< +/-6.144V range = Gain 2/3 | ||
#define ADS1X15_REG_CONFIG_PGA_4_096V (0x0200) ///< +/-4.096V range = Gain 1 | ||
#define ADS1X15_REG_CONFIG_PGA_2_048V \ | ||
(0x0400) ///< +/-2.048V range = Gain 2 (default) | ||
#define ADS1X15_REG_CONFIG_PGA_1_024V (0x0600) ///< +/-1.024V range = Gain 4 | ||
#define ADS1X15_REG_CONFIG_PGA_0_512V (0x0800) ///< +/-0.512V range = Gain 8 | ||
#define ADS1X15_REG_CONFIG_PGA_0_256V (0x0A00) ///< +/-0.256V range = Gain 16 | ||
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#define ADS1X15_REG_CONFIG_MODE_MASK (0x0100) ///< Mode Mask | ||
#define ADS1X15_REG_CONFIG_MODE_CONTIN (0x0000) ///< Continuous conversion mode | ||
#define ADS1X15_REG_CONFIG_MODE_SINGLE \ | ||
(0x0100) ///< Power-down single-shot mode (default) | ||
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#define ADS1X15_REG_CONFIG_RATE_MASK (0x00E0) ///< Data Rate Mask | ||
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#define ADS1X15_REG_CONFIG_CMODE_MASK (0x0010) ///< CMode Mask | ||
#define ADS1X15_REG_CONFIG_CMODE_TRAD \ | ||
(0x0000) ///< Traditional comparator with hysteresis (default) | ||
#define ADS1X15_REG_CONFIG_CMODE_WINDOW (0x0010) ///< Window comparator | ||
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#define ADS1X15_REG_CONFIG_CPOL_MASK (0x0008) ///< CPol Mask | ||
#define ADS1X15_REG_CONFIG_CPOL_ACTVLOW \ | ||
(0x0000) ///< ALERT/RDY pin is low when active (default) | ||
#define ADS1X15_REG_CONFIG_CPOL_ACTVHI \ | ||
(0x0008) ///< ALERT/RDY pin is high when active | ||
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#define ADS1X15_REG_CONFIG_CLAT_MASK \ | ||
(0x0004) ///< Determines if ALERT/RDY pin latches once asserted | ||
#define ADS1X15_REG_CONFIG_CLAT_NONLAT \ | ||
(0x0000) ///< Non-latching comparator (default) | ||
#define ADS1X15_REG_CONFIG_CLAT_LATCH (0x0004) ///< Latching comparator | ||
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#define ADS1X15_REG_CONFIG_CQUE_MASK (0x0003) ///< CQue Mask | ||
#define ADS1X15_REG_CONFIG_CQUE_1CONV \ | ||
(0x0000) ///< Assert ALERT/RDY after one conversions | ||
#define ADS1X15_REG_CONFIG_CQUE_2CONV \ | ||
(0x0001) ///< Assert ALERT/RDY after two conversions | ||
#define ADS1X15_REG_CONFIG_CQUE_4CONV \ | ||
(0x0002) ///< Assert ALERT/RDY after four conversions | ||
#define ADS1X15_REG_CONFIG_CQUE_NONE \ | ||
(0x0003) ///< Disable the comparator and put ALERT/RDY in high state (default) | ||
/*=========================================================================*/ | ||
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/** Gain settings */ | ||
typedef enum { | ||
GAIN_TWOTHIRDS = ADS1X15_REG_CONFIG_PGA_6_144V, | ||
GAIN_ONE = ADS1X15_REG_CONFIG_PGA_4_096V, | ||
GAIN_TWO = ADS1X15_REG_CONFIG_PGA_2_048V, | ||
GAIN_FOUR = ADS1X15_REG_CONFIG_PGA_1_024V, | ||
GAIN_EIGHT = ADS1X15_REG_CONFIG_PGA_0_512V, | ||
GAIN_SIXTEEN = ADS1X15_REG_CONFIG_PGA_0_256V | ||
} adsGain_t; | ||
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/** Data rates */ | ||
#define RATE_ADS1015_128SPS (0x0000) ///< 128 samples per second | ||
#define RATE_ADS1015_250SPS (0x0020) ///< 250 samples per second | ||
#define RATE_ADS1015_490SPS (0x0040) ///< 490 samples per second | ||
#define RATE_ADS1015_920SPS (0x0060) ///< 920 samples per second | ||
#define RATE_ADS1015_1600SPS (0x0080) ///< 1600 samples per second (default) | ||
#define RATE_ADS1015_2400SPS (0x00A0) ///< 2400 samples per second | ||
#define RATE_ADS1015_3300SPS (0x00C0) ///< 3300 samples per second | ||
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#define RATE_ADS1115_8SPS (0x0000) ///< 8 samples per second | ||
#define RATE_ADS1115_16SPS (0x0020) ///< 16 samples per second | ||
#define RATE_ADS1115_32SPS (0x0040) ///< 32 samples per second | ||
#define RATE_ADS1115_64SPS (0x0060) ///< 64 samples per second | ||
#define RATE_ADS1115_128SPS (0x0080) ///< 128 samples per second (default) | ||
#define RATE_ADS1115_250SPS (0x00A0) ///< 250 samples per second | ||
#define RATE_ADS1115_475SPS (0x00C0) ///< 475 samples per second | ||
#define RATE_ADS1115_860SPS (0x00E0) ///< 860 samples per second |
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#pragma once | ||
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#ifdef __cplusplus | ||
extern "C" | ||
{ | ||
#endif | ||
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struct InputState { | ||
int a : 1; | ||
int b : 1; | ||
int x : 1; | ||
int y : 1; | ||
int select : 1; | ||
int start : 1; | ||
int up : 1; | ||
int down : 1; | ||
int left : 1; | ||
int right : 1; | ||
int joystick_select : 1; | ||
}; | ||
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void init_input(); | ||
bool read_joystick(float *x, float *y); | ||
void get_input_state(struct InputState *state); | ||
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#ifdef __cplusplus | ||
} | ||
#endif |
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