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regmap: Break up automatic import chain to avoid pulling on too much
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This change reduces what is imported via the top-level __init__.py file to stop
importing the world. Instead, users should simply import the sub-packages they
need explicitly.
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jranger-es-net committed Jan 21, 2024
1 parent 1a35d98 commit ff37970
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Showing 8 changed files with 24 additions and 14 deletions.
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -3,3 +3,4 @@ dist/
poetry.lock
setup.py
__pycache__
regio-*.bar*.bin
4 changes: 0 additions & 4 deletions src/regio/regmap/__init__.py
Original file line number Diff line number Diff line change
@@ -1,4 +0,0 @@
#---------------------------------------------------------------------------------------------------
from .io import *
from .proxy import *
from .spec import *
5 changes: 3 additions & 2 deletions src/regio/regmap/io/ffi.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
#---------------------------------------------------------------------------------------------------
__all__ = ()

import ctypes as _ctypes, ctypes.util as _cutil
import ctypes as _ctypes
import os

#---------------------------------------------------------------------------------------------------
Expand Down Expand Up @@ -59,6 +59,8 @@ def update(self, ctype, addr, clr_mask, set_mask):
#---------------------------------------------------------------------------------------------------
class LibC:
def __init__(self):
import ctypes.util as _cutil

# Get the C library's path.
# https://docs.python.org/3/library/ctypes.html#finding-shared-libraries
self.path = _cutil.find_library('c')
Expand Down Expand Up @@ -124,4 +126,3 @@ def munmap(self, addr, length):
#---------------------------------------------------------------------------------------------------
# Instantiate on import of the module.
ctype = CType()
libc = LibC()
5 changes: 3 additions & 2 deletions src/regio/regmap/io/mmap.py
Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,7 @@ def __init__(self, path, data_width,
self.page_no = (offset + mmap.PAGESIZE - 1) // mmap.PAGESIZE
self.page_offset = offset % mmap.PAGESIZE
self.mmap_size = mmap_size - self.page_no * mmap.PAGESIZE
self.libc = ffi.LibC()

# Get the C type for accessing a single data word.
self.endian = endian.get()
Expand All @@ -88,7 +89,7 @@ def start(self):

# Map the file's memory region into the virtual address space.
with self.path.open('r+b') as fo:
self._addr_p = ffi.libc.mmap(
self._addr_p = self.libc.mmap(
ffi.ctype.pointer.NULL, self.mmap_size, mmap.PROT_READ | mmap.PROT_WRITE,
mmap.MAP_SHARED, fo.fileno(), self.page_no * mmap.PAGESIZE)

Expand All @@ -101,7 +102,7 @@ def stop(self):
return

# Unmap the memory region from the virtual address space.
ffi.libc.munmap(self._addr_p, self.mmap_size)
self.libc.munmap(self._addr_p, self.mmap_size)
del self._addr_p
del self._base_addr
super().stop()
Expand Down
11 changes: 10 additions & 1 deletion src/regio/regmap/spec/__init__.py
Original file line number Diff line number Diff line change
@@ -1,8 +1,17 @@
#---------------------------------------------------------------------------------------------------
__all__ = (
'AddressSpace',
'Array',
'Access',
'Field',
'Register',
'Structure',
'Union',
)

from .address import AddressSpace
from .array import Array
from .field import Access, Field
from .info import *
from .register import Register
from .structure import Structure
from .union import Union
2 changes: 0 additions & 2 deletions src/regio/regmap/types/__init__.py
Original file line number Diff line number Diff line change
@@ -1,2 +0,0 @@
#---------------------------------------------------------------------------------------------------
__all__ = ()
2 changes: 1 addition & 1 deletion src/regio/tools/templates/block_py.j2
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ __all__ = (
'{{ blk.name_lower }}_block',
)

from regio.regmap import *
from regio.regmap.spec import *

#---------------------------------------------------------------------------------------------------
{%- set data_width = 32 %}{#- TODO: Shouldn't be hardcoded. Get from YAML? #}
Expand Down
8 changes: 6 additions & 2 deletions src/regio/tools/templates/toplevel_py.j2
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,7 @@
#---------------------------------------------------------------------------------------------------
__all__ = ()

import pathlib
from regio.regmap import *
from regio.regmap.spec import AddressSpace
{% for blk in blks.keys() | sort: %}
from .blocks.{{ blk }}_block import *
{%- endfor %}
Expand Down Expand Up @@ -61,6 +60,11 @@ __all__ += (
)
{% endfor %}
#---------------------------------------------------------------------------------------------------
import pathlib

from regio.regmap.io import DevMmapIOForSpec
from regio.regmap.proxy import for_io_by_path

PCI_DEVICES_DIR = pathlib.Path('/sys/bus/pci/devices')

def _hex_to_int(path):
Expand Down

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